Issued Patents All Time
Showing 26–34 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10318294 | Operation of a multi-slice processor implementing dependency accumulation instruction sequencing | Khandker N. Adeeb, Jeffrey C. Brownscheidle, Brandon Goddard, Dung Q. Nguyen, Tu-An T. Nguyen +2 more | 2019-06-11 |
| 10248426 | Direct register restore mechanism for distributed history buffers | Brian D. Barrick, Steven J. Battle, Christopher M. Mueller, Dung Q. Nguyen, David R. Terry +2 more | 2019-04-02 |
| 10248421 | Operation of a multi-slice processor with reduced flush and restore latency | Salma Ayub, Brian D. Barrick, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen +2 more | 2019-04-02 |
| 10241790 | Operation of a multi-slice processor with reduced flush and restore latency | Salma Ayub, Brian D. Barrick, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen +2 more | 2019-03-26 |
| 9959123 | Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor | Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry +1 more | 2018-05-01 |
| 9928073 | Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor | Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry +1 more | 2018-03-27 |
| 9921833 | Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor | Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry +1 more | 2018-03-20 |
| 9858078 | Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor | Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry +1 more | 2018-01-02 |
| 9639418 | Parity protection of a register | Sam Gat-Shang Chu, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen, David R. Terry | 2017-05-02 |