Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7613050 | Sense-amplifier assist (SAA) with power-reduction technique | Harold Pilo, Fred J. Towler | 2009-11-03 |
| 7573300 | Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same | Wagdi W. Abadeer, Albert M. Chu, John A. Fifield, Harold Pilo, Daryl M. Seitzer | 2009-08-11 |
| 7471114 | Design structure for a current control mechanism for power networks and dynamic logic keeper circuits | Wagdi W. Abadeer, Albert M. Chu, John A. Fifield, Harold Pilo, Daryl M. Seitzer | 2008-12-30 |
| 7408800 | Apparatus and method for improved SRAM device performance through double gate topology | Wilfried Haensch, Joseph A. Iadanza | 2008-08-05 |
| 7337268 | Content addressable memory structure | Robert E. Busch | 2008-02-26 |
| 7307457 | Apparatus for implementing dynamic data path with interlocked keeper and restore devices | John A. Fifield, Harold Pilo | 2007-12-11 |
| 7180320 | Adaptive integrated circuit based on transistor current measurements | Harold Pilo | 2007-02-20 |
| 7120732 | Content addressable memory structure | Robert E. Busch | 2006-10-10 |
| 7061793 | Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices | John E. Barth, Jr., Harold Pilo | 2006-06-13 |
| 6999547 | Delay-lock-loop with improved accuracy and range | Harold Pilo | 2006-02-14 |
| 6967861 | Method and apparatus for improving cycle time in a quad data rate SRAM device | Harold Pilo | 2005-11-22 |
| 6922076 | Scalable termination | Reid C. Hutchins, Harold Pilo | 2005-07-26 |
| 6897674 | Adaptive integrated circuit based on transistor current measurements | Harold Pilo | 2005-05-24 |
| 6829183 | Active restore weak write test mode | — | 2004-12-07 |
| 6754791 | Cache memory system and method for accessing a cache memory having a redundant array without displacing a cache line in a main array | Lawrence Howell | 2004-06-22 |
| 6711076 | Active restore weak write test mode | — | 2004-03-23 |
| 6650580 | Method for margin testing | — | 2003-11-18 |
| 6542418 | Redundant memory array having dual-use repair elements | Patrick R. Hansen | 2003-04-01 |
| 6509778 | BIST circuit for variable impedance system | Steven Burns, Patrick R. Hansen, Harold Pilo | 2003-01-21 |
| 6510091 | Dynamic precharge decode scheme for fast DRAM | Harold Pilo | 2003-01-21 |
| 6501293 | Method and apparatus for programmable active termination of input/output devices | John Connor, Patrick R. Hansen | 2002-12-31 |
| 6441646 | Structure and method of alternating precharge in dynamic SOI circuits | Patrick R. Hansen | 2002-08-27 |
| 6392949 | High performance memory architecture | Harold Pilo | 2002-05-21 |
| 6038181 | Efficient semiconductor burn-in circuit and method of operation | James J. Covino, Richard E. Hee, Harold Pilo | 2000-03-14 |
| 5929667 | Method and apparatus for protecting circuits subjected to high voltage | Wagdi W. Abadeer, John Connor, Donald Albert Evans | 1999-07-27 |