Issued Patents All Time
Showing 26–50 of 362 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11106608 | Synchronizing access to shared memory by extending protection for a target address of a store-conditional request | Guy L. Guthrie, Hugh Shen, Sanjeev Ghai | 2021-08-31 |
| 11086672 | Low latency management of processor core wait state | Hugh Shen, Guy L. Guthrie | 2021-08-10 |
| 11068407 | Synchronized access to data in shared memory by protecting the load target address of a load-reserve instruction | Guy L. Guthrie | 2021-07-20 |
| 11030110 | Integrated circuit and data processing system supporting address aliasing in an accelerator | Michael S. Siegel, Bartholomew Blaner, Jeffrey A. Stuecheli, William J. Starke, Kenneth M. Valk +2 more | 2021-06-08 |
| 10997075 | Adaptively enabling and disabling snooping bus commands | Guy L. Guthrie, Hien Minh Le, Hugh Shen, Phillip G. Williams | 2021-05-04 |
| 10977035 | Atomic memory operation having selectable location of performance | Guy L. Guthrie | 2021-04-13 |
| 10977183 | Processing a sequence of translation entry invalidation requests with regard to draining a processor core | Guy L. Guthrie, Hugh Shen | 2021-04-13 |
| 10970215 | Cache snooping mode extending coherence protection for certain requests | Guy L. Guthrie, Hugh Shen, Luke Murray | 2021-04-06 |
| 10956070 | Zeroing a memory block without processor caching | Guy L. Guthrie, Hugh Shen | 2021-03-23 |
| 10949346 | Data flush of a persistent memory cache or buffer | Guy L. Guthrie, John Steven Dodson | 2021-03-16 |
| 10884740 | Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads | Guy L. Guthrie, Kimberly M. Fernsler, Hugh Shen | 2021-01-05 |
| 10831607 | Dynamic transaction throttling in a data processing system supporting transactional memory | Guy L. Guthrie, Hugh Shen, Sanjeev Ghai, Hung Q. Doan | 2020-11-10 |
| 10831660 | Ordering execution of an interrupt handler | Guy L. Guthrie, Hugh Shen | 2020-11-10 |
| 10824567 | Selectively preventing pre-coherence point reads in a cache hierarchy to reduce barrier overhead | Hugh Shen, Guy L. Guthrie, William J. Starke | 2020-11-03 |
| 10817434 | Interruptible translation entry invalidation in a multithreaded data processing system | Benjamin Herrenschmidt, Cathy May, Bradly G. Frey | 2020-10-27 |
| 10740239 | Translation entry invalidation in a multithreaded data processing system | Guy L. Guthrie, Hugh Shen | 2020-08-11 |
| 10733102 | Selectively updating a coherence state in response to a storage update | Guy L. Guthrie | 2020-08-04 |
| 10725937 | Synchronized access to shared memory by extending protection for a store target address of a store-conditional request | Guy L. Guthrie, Hugh Shen, Sanjeev Ghai | 2020-07-28 |
| 10713169 | Remote node broadcast of requests in a multinode data processing system | Eric E. Retter, Michael S. Siegel, Jeffrey A. Stuecheli | 2020-07-14 |
| 10705957 | Selectively updating a coherence state in response to a storage update | Guy L. Guthrie | 2020-07-07 |
| 10691605 | Expedited servicing of store operations in a data processing system | Guy L. Guthrie, Hugh Shen, Jeffrey A. Stuecheli | 2020-06-23 |
| 10691599 | Selectively updating a coherence state in response to a storage update | Guy L. Guthrie | 2020-06-23 |
| 10635766 | Simulation employing level-dependent multitype events | Guy L. Guthrie, Hugh Shen | 2020-04-28 |
| 10613980 | Coherence protocol providing speculative coherence response to directory probe | Guy L. Guthrie, David J. Krolak, Michael S. Siegel | 2020-04-07 |
| 10613979 | Accelerator memory coherency with single state machine | Kenneth M. Valk, Guy L. Guthrie, Michael S. Siegel, John D. Irish | 2020-04-07 |