Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9576863 | Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughness | Shawn A. Adderly, Kyle Babinski, David A. DeMuynck, Shawn R. Goddard, Matthew D. Moon +2 more | 2017-02-21 |
| 9330988 | Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughness | Shawn A. Adderly, Kyle Babinski, David A. DeMuynck, Shawn R. Goddard, Matthew D. Moon +2 more | 2016-05-03 |
| 9087839 | Semiconductor structures with metal lines | Shawn A. Adderly, Zhong-Xiang He, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan +2 more | 2015-07-21 |
| 9006703 | Method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof | Shawn A. Adderly, Brian M. Czabaj, Jeffrey P. Gambino, Matthew D. Moon, David C. Thomas | 2015-04-14 |
| 8084864 | Electromigration resistant aluminum-based metal interconnect structure | Jonathan D. Chapple-Sokol, Zhong-Xiang He, Tom C. Lee, William J. Murphy, Timothy D. Sullivan +2 more | 2011-12-27 |
| 8003536 | Electromigration resistant aluminum-based metal interconnect structure | Jonathan D. Chapple-Sokol, Zhong-Xiang He, Tom C. Lee, William J. Murphy, Timothy D. Sullivan +2 more | 2011-08-23 |