Issued Patents All Time
Showing 26–50 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10453517 | High capacity memory system using controller component | Frederick A. Ware, Scott C. Best | 2019-10-22 |
| 10455698 | Load reduced memory module | Frederick A. Ware | 2019-10-22 |
| 10402352 | Semiconductor memory systems with on-die data buffering | Frederick A. Ware, Amir Amirkhany, Mohammad Hekmat, Dinesh Patil | 2019-09-03 |
| 10380053 | Folded memory modules | Amir Amirkhany, Ravindranath Kollipara, Ian Shaeffer, David A. Secker | 2019-08-13 |
| 10223299 | High capacity memory system with improved command-address and chip-select signaling mode | Frederick A. Ware, Abhijit M. Abhyankar | 2019-03-05 |
| 10198314 | Memory device with in-system repair capability | Frederick A. Ware, Brent Haukness, Scott C. Best, Wayne F. Ellis | 2019-02-05 |
| 10149383 | Load reduced memory module | Frederick A. Ware | 2018-12-04 |
| 10013371 | Configurable memory circuit system and method | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2018-07-03 |
| 9837132 | High capacity memory system | Frederick A. Ware | 2017-12-05 |
| 9826638 | Load reduced memory module | Frederick A. Ware | 2017-11-21 |
| 9734921 | Memory repair using external tags | Frederick A. Ware, Ian Shaeffer | 2017-08-15 |
| 9727458 | Translating an address associated with a command communicated between a system and memory circuits | David T. Wang, Keith R. Schakel, Michael J. Smith, Frederick Daniel Weber | 2017-08-08 |
| 9691504 | DRAM retention test method for dynamic error correction | Ely Tsern, Frederick A. Ware, Thomas Vogelsang | 2017-06-27 |
| 9653146 | High capacity memory system using standard controller component | Frederick A. Ware, Scott C. Best | 2017-05-16 |
| 9632929 | Translating an address associated with a command communicated between a system and memory circuits | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2017-04-25 |
| 9575835 | Error correction in a memory device | Thomas Vogelsang, Ian Shaeffer, Frederick A. Ware, Wayne F. Ellis | 2017-02-21 |
| 9542353 | System and method for reducing command scheduling constraints of memory circuits | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2017-01-10 |
| 9542352 | System and method for reducing command scheduling constraints of memory circuits | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2017-01-10 |
| 9507739 | Configurable memory circuit system and method | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2016-11-29 |
| 9501433 | Semiconductor memory systems with on-die data buffering | Frederick A. Ware, Amir Amirkhany, Mohammad Hekmat, Dinesh Patil | 2016-11-22 |
| 9489323 | Folded memory modules | Amir Amirkhany, Ravindranath Kollipara, Ian Shaeffer, David A. Secker | 2016-11-08 |
| 9411678 | DRAM retention monitoring method for dynamic error correction | Frederick A. Ware, Ely Tsern, Thomas Vogelsang, Wayne F. Ellis | 2016-08-09 |
| 9232651 | Load reduced memory module | Frederick A. Ware | 2016-01-05 |
| 9183920 | High capacity memory system using standard controller component | Frederick A. Ware, Scott C. Best | 2015-11-10 |
| 9171585 | Configurable memory circuit system and method | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2015-10-27 |