Issued Patents All Time
Showing 51–75 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9165639 | High capacity memory system using standard controller component | Frederick A. Ware, Scott C. Best | 2015-10-20 |
| 9047976 | Combined signal delay and power saving for use with a plurality of memory circuits | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2015-06-02 |
| 9037949 | Error correction in a memory device | Thomas Vogelsang, Ian Shaeffer, Frederick A. Ware, Wayne F. Ellis | 2015-05-19 |
| 9009400 | Semiconductor memory systems with on-die data buffering | Frederick A. Ware, Amir Amirkhany, Mohammad Hekmat, Dinesh Patil | 2015-04-14 |
| 8972673 | Power management of memory circuits by virtual memory simulation | Michael J. Smith, David T. Wang | 2015-03-03 |
| 8949519 | Simulating a memory circuit | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2015-02-03 |
| 8868829 | Memory circuit system and method | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2014-10-21 |
| 8819356 | Configurable multirank memory system with interface circuit | David T. Wang | 2014-08-26 |
| 8811065 | Performing error detection on DRAMs | Michael J. Smith, David T. Wang | 2014-08-19 |
| 8797779 | Memory module with memory stack and interface with enhanced capabilites | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2014-08-05 |
| 8773937 | Memory refresh apparatus and method | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2014-07-08 |
| 8762675 | Memory system for synchronous data transmission | David T. Wang | 2014-06-24 |
| 8760936 | Multi-rank partial width memory modules | Michael J. Smith | 2014-06-24 |
| 8751732 | System and method for increasing capacity, performance, and flexibility of flash storage | Radoslav Danilak, Michael J.S. Smith | 2014-06-10 |
| 8745321 | Simulating a memory standard | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2014-06-03 |
| 8675429 | Optimal channel design for memory devices for providing a high-speed memory interface | Min Wang, Philip Ferolito, Michael J. Smith | 2014-03-18 |
| 8671244 | Simulating a memory standard | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2014-03-11 |
| 8667312 | Performing power management operations | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2014-03-04 |
| 8631193 | Emulation of abstracted DIMMS using abstracted DRAMS | Michael J. Smith, David T. Wang | 2014-01-14 |
| 8631220 | Adjusting the timing of signals associated with a memory system | Michael J. Smith, Daniel L. Rosenband, David T. Wang | 2014-01-14 |
| 8619452 | Methods and apparatus of stacking DRAMs | Michael J. Smith, David T. Wang | 2013-12-31 |
| 8615679 | Memory modules with reliability and serviceability functions | Michael J. Smith | 2013-12-24 |
| 8601204 | Simulating a refresh operation latency | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2013-12-03 |
| 8595419 | Memory apparatus operable to perform a power-saving operation | Keith R. Schakel, Michael J. Smith, David T. Wang, Frederick Daniel Weber | 2013-11-26 |
| 8582339 | System including memory stacks | — | 2013-11-12 |