Issued Patents All Time
Showing 26–50 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10504774 | Lithographic patterning to form fine pitch features | Sohan S. Mehta, SherJang Singh, Ravi Prakash Srivastava | 2019-12-10 |
| 10497610 | Dual photoresist approach to lithographic patterning for pitch reduction | Ravi Prakash Srivastava | 2019-12-03 |
| 10453605 | Insulating inductor conductors with air gap using energy evaporation material (EEM) | Jagar Singh | 2019-10-22 |
| 10353288 | Litho-litho-etch double patterning method | Vineet Sharma, Sohan S. Mehta, Craig D. Higgins, Feng Wang | 2019-07-16 |
| 10347528 | Interconnect formation process using wire trench etch prior to via etch, and related interconnect | Ravi Prakash Srivastava, Sipeng Gu, Akshey Sehgal | 2019-07-09 |
| 10312136 | Etch damage and ESL free dual damascene metal interconnect | Chung-Ju Lee, Tien-I Bao | 2019-06-04 |
| 10312188 | Interconnect structure with method of forming the same | Ravi Prakash Srivastava | 2019-06-04 |
| 10177029 | Integration of air gaps with back-end-of-line structures | Robert J. Fox | 2019-01-08 |
| 10169156 | Automatic restarting of containers | Rajat Verma | 2019-01-01 |
| 10111427 | Formulation for improving the yield and quality of fiber in cotton plants | Samir Viswanath Sawant, Babita Singh, Parthasarathi Bhattacharya | 2018-10-30 |
| 10109706 | Method of forming high performance vertical natural capacitor (VNCAP) | Devender, M. Golam Faruk, Dewei Xu | 2018-10-23 |
| 10083904 | Metholodogy for profile control and capacitance reduction | Shesh Mani Pandey | 2018-09-25 |
| 10084093 | Low resistance conductive contacts | Shiv Kumar Mishra, Shesh Mani Pandey | 2018-09-25 |
| 9960113 | Method to fabricate a high performance capacitor in a back end of line (BEOL) | Shesh Mani Pandey | 2018-05-01 |
| 9786549 | Etch damage and ESL free dual damascene metal interconnect | Chung-Ju Lee, Tien-I Bao | 2017-10-10 |
| 9741605 | Reducing defects and improving reliability of BEOL metal fill | — | 2017-08-22 |
| 9711346 | Method to fabricate a high performance capacitor in a back end of line (BEOL) | Shesh Mani Pandey | 2017-07-18 |
| 9691654 | Methods and devices for back end of line via formation | Sohan S. Mehta, Ravi Prakash Srivastava | 2017-06-27 |
| 9613909 | Methods and devices for metal filling processes | Ravi Prakash Srivastava, Nicholas Robert STOKES | 2017-04-04 |
| 9593119 | Process for the preparation of dipeptidylpeptidase inhibitors | Sachin Srivastava, Shekhar Bhaskar Bhirud | 2017-03-14 |
| 9576894 | Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same | Ravi Prakash Srivastava, Xusheng Wu, Akshey Sehgal, Teck Jung Tang | 2017-02-21 |
| 9530553 | High performance inductor/transformer and methods of making such inductor/transformer structures | Jagar Singh, Pankaj Marria | 2016-12-27 |
| 9524935 | Filling cavities in an integrated circuit and resulting devices | Jonathan Rullan | 2016-12-20 |
| 9362162 | Methods of fabricating BEOL interlayer structures | Ravi Prakash Srivastava, Teck Jung Tang, Mark A. Zaleski | 2016-06-07 |
| 9353114 | Process for the preparation of dipeptidylpeptidase inhibitors | Sachin Srivastava, Shekhar Bhaskar Bhirud | 2016-05-31 |