Issued Patents All Time
Showing 101–125 of 173 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9779987 | Titanium silicide formation in a narrow source-drain contact | Kwanyong LIM, Hiroaki Niimi | 2017-10-03 |
| 9761495 | Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices | Ruilong Xie, Catherine B. Labelle, Chanro Park, Hoon Kim | 2017-09-12 |
| 9741623 | Dual liner CMOS integration methods for FinFET devices | Chanro Park, Ruilong Xie, Hoon Kim | 2017-08-22 |
| 9732315 | Axenic inoculation system for microalgae using TR tube of triiodide resin and method for culturing axenic culture | Jong-Hee KWON, Ji Won YANG, Ju-Young Jung, Gi Bok Nam, Min Sung Park +1 more | 2017-08-15 |
| 9735063 | Methods for forming fin structures | Chanro Park, Hoon Kim, Ruilong Xie | 2017-08-15 |
| 9735242 | Semiconductor device with a gate contact positioned above the active region | Ruilong Xie, Chanro Park, Hoon Kim | 2017-08-15 |
| 9735060 | Hybrid fin cut etching processes for products comprising tapered and non-tapered FinFET semiconductor devices | Ruilong Xie, Chanro Park, Hoon Kim | 2017-08-15 |
| 9735061 | Methods to form multi threshold-voltage dual channel without channel doping | Hoon Kim, Ruilong Xie, Chanro Park | 2017-08-15 |
| 9722024 | Formation of semiconductor structures employing selective removal of fins | Ruilong Xie, Catherine B. Labelle | 2017-08-01 |
| 9722053 | Methods, apparatus and system for local isolation formation for finFET devices | Ruilong Xie, Hoon Kim, Chanro Park, Sukwon Hong | 2017-08-01 |
| 9691664 | Dual thick EG oxide integration under aggressive SG fin pitch | Chanro Park, Hoon Kim, Ruilong Xie | 2017-06-27 |
| 9685522 | Forming uniform WF metal layers in gate areas of nano-sheet structures | Hoon Kim, Ruilong Xie, Chanro Park | 2017-06-20 |
| 9653356 | Methods of forming self-aligned device level contact structures | Chanro Park, Ruilong Xie, Hoon Kim | 2017-05-16 |
| 9646884 | Block level patterning process | Chanro Park, Sukwon Hong, Hoon Kim | 2017-05-09 |
| 9627535 | Semiconductor devices with an etch stop layer on gate end-portions located above an isolation region | Ruilong Xie, Hoon Kim, Chanro Park | 2017-04-18 |
| 9613962 | Fin liner integration under aggressive pitch | Neeraj Tripathi | 2017-04-04 |
| 9595583 | Methods for forming FinFETS having a capping layer for reducing punch through leakage | Hoon Kim | 2017-03-14 |
| 9552992 | Co-fabrication of non-planar semiconductor devices having different threshold voltages | Hoon Kim, Chanro Park, Ruilong Xie | 2017-01-24 |
| 9548249 | Methods of performing fin cut etch processes for FinFET semiconductor devices and the resulting devices | Catherine B. Labelle | 2017-01-17 |
| 9543416 | Methods of forming products with FinFET semiconductor devices without removing fins in certain areas of the product | Ryan Ryoung-Han Kim | 2017-01-10 |
| 9508604 | Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers | Chanro Park, Hoon Kim, Ruilong Xie | 2016-11-29 |
| 9502286 | Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices | Ruilong Xie, Chanro Park, Hoon Kim, Andre P. Labonte | 2016-11-22 |
| 9502308 | Methods for forming transistor devices with different source/drain contact liners and the resulting devices | Chanro Park, Hoon Kim, Ruilong Xie | 2016-11-22 |
| 9478538 | Methods for forming transistor devices with different threshold voltages and the resulting devices | Hoon Kim, Ruilong Xie, Chanro Park | 2016-10-25 |
| 9478661 | Semiconductor device structures with self-aligned fin structure(s) and fabrication methods thereof | Ruilong Xie, Chanro Park, Hoon Kim | 2016-10-25 |