Issued Patents All Time
Showing 126–150 of 173 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9449881 | Methods of forming fins for FinFET semiconductor devices and the resulting devices | Ruilong Xie | 2016-09-20 |
| 9425106 | Methods of performing fin cut etch processes for taper FinFET semiconductor devices and the resulting devices | Ruilong Xie, Chanro Park, Hoon Kim | 2016-08-23 |
| 9419131 | Semiconductor device having vertical channel transistor and method for fabricating the same | Yong-Soo Kim, Kwan-Yong Lim | 2016-08-16 |
| 9412616 | Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products | Ruilong Xie, Kwan-Yong Lim, Ryan Ryoung-Han Kim | 2016-08-09 |
| 9391174 | Method of uniform fin recessing using isotropic etch | Ruilong Xie, Chanro Park, Hoon Kim | 2016-07-12 |
| 9385189 | Fin liner integration under aggressive pitch | Neeraj Tripathi | 2016-07-05 |
| 9379017 | Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay mark | Chanro Park, Hoon Kim, Ruilong Xie | 2016-06-28 |
| 9362181 | Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products | Ruilong Xie, Ryan Ryoung-Han Kim, Kwan-Yong Lim, Chanro Park | 2016-06-07 |
| 9362377 | Low line resistivity and repeatable metal recess using CVD cobalt reflow | Hoon Kim, Vimal Kamineni, Chanro Park | 2016-06-07 |
| 9337101 | Methods for selectively removing a fin when forming FinFET devices | Hoon Kim, Chanro Park, Ruilong Xie | 2016-05-10 |
| 9324799 | FinFET structures having uniform channel size and methods of fabrication | Kwan-Yong Lim, Sukwon Hong | 2016-04-26 |
| 9312182 | Forming gate and source/drain contact openings by performing a common etch patterning process | Ruilong Xie, William J. Taylor, Jr. | 2016-04-12 |
| 9312388 | Methods of forming epitaxial semiconductor material in trenches located above the source and drain regions of a semiconductor device | Ruilong Xie, Hoon Kim, Chanro Park | 2016-04-12 |
| 9312183 | Methods for forming FinFETS having a capping layer for reducing punch through leakage | Hoon Kim | 2016-04-12 |
| 9263446 | Methods of forming replacement gate structures on transistor devices with a shared gate structure and the resulting products | Ruilong Xie, Kwan-Yong Lim, Chanro Park | 2016-02-16 |
| 9236308 | Methods of fabricating fin structures of uniform height | Kwan-Yong Lim, Sukwon Hong | 2016-01-12 |
| 9190488 | Methods of forming gate structure of semiconductor devices and the resulting devices | Chanro Park, Hoon Kim | 2015-11-17 |
| 9178035 | Methods of forming gate structures of semiconductor devices | Chanro Park, Hoon Kim | 2015-11-03 |
| 9064854 | Semiconductor device with gate stack structure | Kwan-Yong Lim, Hong-Seon Yang, Heung-Jae Cho, Tae Kyung Kim, Yong-Soo Kim | 2015-06-23 |
| 8847322 | Dual polysilicon gate of a semiconductor device with a multi-plane channel | Kwan-Yong Lim, Heung-Jae Cho | 2014-09-30 |
| 8760920 | Semiconductor memory device integrating flash memory and resistive/magnetic memory | Sook-Joo Kim | 2014-06-24 |
| 8759906 | Semiconductor device having vertical channel transistor and method for fabricating the same | Yong-Soo Kim, Kwan-Yong Lim | 2014-06-24 |
| 8592899 | Transistor having vertical channel | Se-Aug Jang, Hong-Seon Yang, Heung-Jae Cho, Tae Yoon Kim, Sook-Joo Kim | 2013-11-26 |
| 8471338 | Dual polysilicon gate of a semiconductor device with a multi-plane channel | Kwan-Yong Lim, Heung-Jae Cho | 2013-06-25 |
| 8440560 | Method for fabricating tungsten line and method for fabricating gate of semiconductor device using the same | Heung-Jae Cho, Kwan-Yong Lim | 2013-05-14 |