Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7434264 | Data processing system with peripheral access protection and method therefor | William C. Moyer, Craig D. Shaw | 2008-10-07 |
| 6766433 | System having user programmable addressing modes and method therefor | Daniel M. McCarthy, Henri Cloetens, Nancy H. Woo, Bridget Catherine Hooser | 2004-07-20 |
| 6192449 | Apparatus and method for optimizing performance of a cache memory in a data processing system | Anup S. Tirumala, Vasudev Bibikar | 2001-02-20 |
| 6035422 | Data processing system for controlling execution of a debug function and method therefor | William A. Hohl | 2000-03-07 |
| 6026501 | Data processing system for controlling execution of a debug function and method thereof | William A. Hohl | 2000-02-15 |
| 5964893 | Data processing system for performing a trace function and method therefor | Klaus R. Riedel | 1999-10-12 |
| 5911151 | Optimizing block-sized operand movement utilizing standard instructions | James Nolan Hardage, Glen Andrew Harris | 1999-06-08 |
| 5872940 | Programmable read/write access signal and method therefor | James G. Gay, Clinton Thomas Glover, Kevin Traynor | 1999-02-16 |
| 5765190 | Cache memory in a data processing system | Anup S. Tirumala, Vasudev Bibikar | 1998-06-09 |
| 5761491 | Data processing system and method for storing and restoring a stack pointer | Jefferson L. Gokingco | 1998-06-02 |
| 5737516 | Data processing system for performing a debug function and method therefor | William A. Hohl | 1998-04-07 |
| 5704034 | Method and circuit for initializing a data processing system | — | 1997-12-30 |
| 5666509 | Data processing system for performing either a precise memory access or an imprecise memory access based upon a logical address value and method thereof | Daniel M. McCarthy, Richard Duerden, Gregory C. Edgington, Cliff L. Parrott, William B. Ledbetter, Jr. | 1997-09-09 |
| 5592493 | Serial scan chain architecture for a data processing system and method of operation | Alfred L. Crouch, Matthew D. Pressly, Richard Duerden | 1997-01-07 |
| 5592634 | Zero-cycle multi-state branch cache prediction data processing system and method thereof | David J. Schimke | 1997-01-07 |
| 5530804 | Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes | Gregory C. Edgington, Daniel M. McCarthy, Richard Duerden | 1996-06-25 |
| 5471625 | Method and apparatus for entering a low-power mode and controlling an external bus of a data processing system during low-power mode | Gary A. Mussemann, James G. Gay | 1995-11-28 |
| 5131086 | Method and system for executing pipelined three operand construct | Richard Duerden, Roger W. Luce, Ralph H. Olson | 1992-07-14 |
| 5101341 | Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO | Richard Duerden, Roger W. Luce, Ralph H. Olson | 1992-03-31 |
| 5029070 | Coherent cache structures and methods | Daniel M. McCarthy, Gabriel R. Munguia, Nicholas J. Richardson | 1991-07-02 |
| 4928225 | Coherent cache structures and methods | Daniel M. McCarthy, Gabriel R. Munguia, Nicholas J. Richardson | 1990-05-22 |
| 4602368 | Dual validity bit arrays | John E. Wilhite, William A. Shelly, Morgan S. Riley | 1986-07-22 |
| 4597044 | Apparatus and method for providing a composite descriptor in a data processing system | — | 1986-06-24 |
| 4594660 | Collector | Russell W. Guenthner, Gregory C. Edgington, Leonard G. Trubisky | 1986-06-10 |
| 4538237 | Method and apparatus for calculating the residue of a binary number | — | 1985-08-27 |