Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6970977 | Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment | Wayne R. Buzby, Charles P. Ryan, Robert J. Baryla, Lowell D. McCulley | 2005-11-29 |
| 6898738 | High integrity cache directory | Charles P. Ryan, Stephen A. Schuerich | 2005-05-24 |
| 6754859 | Computer processor read/alter/rewrite optimization cache invalidate signals | Bruce E. Hayden | 2004-06-22 |
| 6530076 | Data processing system processor dynamic selection of internal signal tracing | Charles P. Ryan, Ron Yoder | 2003-03-04 |
| 6484272 | Gate close balking for fair gating in a nonuniform memory architecture data processing system | David A. Egolf, Wayne R. Buzby | 2002-11-19 |
| 6480973 | Gate close failure notification for fair gating in a nonuniform memory architecture data processing system | David A. Egolf, Wayne R. Buzby | 2002-11-12 |
| 6351807 | Data processing system utilizing multiple resister loading for fast domain switching | Ron Yoder, Russell W. Guenthner, Eric Conway, Boubaker Shaiek, Claude Rabel | 2002-02-26 |
| 6249880 | Method and apparatus for exhaustively testing interactions among multiple processors | Charles P. Ryan | 2001-06-19 |
| 6230263 | Data processing system processor delay instruction | Charles P. Ryan, Ronald W. Yoder | 2001-05-08 |
| 6223228 | Apparatus for synchronizing multiple processors in a data processing system | Charles P. Ryan, Ronald W. Yoder | 2001-04-24 |
| 6052700 | Calendar clock caching in a multiprocessor data processing system | Clinton B. Eckard | 2000-04-18 |
| 6006309 | Information block transfer management in a multiprocessor computer system employing private caches for individual center processor units and a shared cache | Minoru Inoshita, Robert J. Baryla | 1999-12-21 |
| 5963973 | Multiprocessor computer system incorporating method and apparatus for dynamically assigning ownership of changeable data | Elisabeth Vanhove, Minoru Inoshita, Robert J. Baryla | 1999-10-05 |
| 5829029 | Private cache miss and access management in a multiprocessor system with shared memory | Robert J. Baryla, Minoru Inoshita | 1998-10-27 |
| 5649090 | Fault tolerant multiprocessor computer system | David Scott Edwards, Jiuyih Chang, Minoru Inoshita, Leonard G. Trubisky | 1997-07-15 |
| 5644761 | Basic operations synchronization and local mode controller in a VLSI central processor | Ronald W. Yoder, Ronald Lange, Russell W. Guenthner, Richard L. Demers | 1997-07-01 |
| 5515529 | Central processor with duplicate basic processing units employing multiplexed data signals to reduce inter-unit conductor count | Ronald Lange, Donald C. Boothroyd | 1996-05-07 |
| 5495579 | Central processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor count | Ronald Lange, Donald C. Boothroyd | 1996-02-27 |
| 5276862 | Safestore frame implementation in a central processor | Lowell D. McCulley, Russell W. Guenthner, Clinton B. Eckard, Leonard Rabins, Ronald Lange +1 more | 1994-01-04 |
| 5263034 | Error detection in the basic processing unit of a VLSI central processor | Russell W. Guenthner, Clinton B. Eckard, Leonard Rabins, Ronald Lange, David Scott Edwards +1 more | 1993-11-16 |
| 5251321 | Binary to binary coded decimal and binary coded decimal to binary conversion in a VLSI central processing unit | Donald C. Boothroyd, Clinton B. Eckard, Ronald Lange, Ronald W. Yoder | 1993-10-05 |
| 4858176 | Distributor of machine words between units of a central processor | John E. Wilhite | 1989-08-15 |
| 4602368 | Dual validity bit arrays | Joseph C. Circello, John E. Wilhite, Morgan S. Riley | 1986-07-22 |
| 4594659 | Method and apparatus for prefetching instructions for a central execution pipeline unit | Russell W. Guenthner, Gary R. Presley-Nelson, Kala J. Marietta, R. Morse Wade | 1986-06-10 |
| 4521850 | Instruction buffer associated with a cache memory unit | John E. Wilhite, Charles P. Ryan | 1985-06-04 |