Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6973539 | Multiprocessor write-into-cache system incorporating efficient access to a plurality of gatewords | Wayne R. Buzby | 2005-12-06 |
| 6970977 | Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment | Wayne R. Buzby, Robert J. Baryla, William A. Shelly, Lowell D. McCulley | 2005-11-29 |
| 6898738 | High integrity cache directory | William A. Shelly, Stephen A. Schuerich | 2005-05-24 |
| 6868483 | Balanced access to prevent gateword dominance in a multiprocessor write-into-cache environment | Wayne R. Buzby | 2005-03-15 |
| 6760811 | Gateword acquisition in a multiprocessor write-into-cache environment | Wayne R. Buzby | 2004-07-06 |
| 6604060 | Method and apparatus for determining CC-NUMA intra-processor delays | Eric Conway | 2003-08-05 |
| 6530076 | Data processing system processor dynamic selection of internal signal tracing | Ron Yoder, William A. Shelly | 2003-03-04 |
| 6442681 | Pipelined central processor managing the execution of instructions with proximate successive branches in a cache-based data processing system while performing block mode transfer predictions | Patrice Brossard | 2002-08-27 |
| 6363474 | Process switching register replication in a data processing system | Lowell D. McCulley, Ronald W. Yoder | 2002-03-26 |
| 6249880 | Method and apparatus for exhaustively testing interactions among multiple processors | William A. Shelly | 2001-06-19 |
| 6230263 | Data processing system processor delay instruction | Ronald W. Yoder, William A. Shelly | 2001-05-08 |
| 6223228 | Apparatus for synchronizing multiple processors in a data processing system | William A. Shelly, Ronald W. Yoder | 2001-04-24 |
| 6175897 | Synchronization of branch cache searches and allocation/modification/deletion of branch cache | Patrice Brossard | 2001-01-16 |
| 5701426 | Data processing system and method using cache miss address prediction and forced LRU status in a cache memory to improve cache hit ratio | — | 1997-12-23 |
| 5694572 | Controllably operable method and apparatus for predicting addresses of future operand requests by examination of addresses of prior cache misses | — | 1997-12-02 |
| 5495591 | Method and system for cache miss prediction based on previous cache access requests | — | 1996-02-27 |
| 5450561 | Cache miss prediction method and apparatus for use with a paged main memory in a data processing system | — | 1995-09-12 |
| 5426764 | Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor | — | 1995-06-20 |
| 5367656 | Controlling cache predictive prefetching based on cache hit ratio trend | — | 1994-11-22 |
| 5093777 | Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack | — | 1992-03-03 |
| 5018075 | Unknown response processing in a diagnostic expert system | Thomas H. Howell, Andrew Y. Pan, David W. Rolston | 1991-05-21 |
| 4707784 | Prioritized secondary use of a cache with simultaneous access | Russell W. Guenthner | 1987-11-17 |
| 4551799 | Verification of real page numbers of stack stored prefetched instructions from instruction cache | Russell W. Guenthner | 1985-11-05 |
| 4527238 | Cache with independent addressable data and directory arrays | Russell W. Guenthner, Leonard G. Trubisky | 1985-07-02 |
| 4521850 | Instruction buffer associated with a cache memory unit | John E. Wilhite, William A. Shelly | 1985-06-04 |