Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5859541 | Data processor having an output terminal with selectable output impedances | Steven C. McMahan, Kenneth C. Scheuer, Michael G. Gallup, James G. Gay | 1999-01-12 |
| 5666509 | Data processing system for performing either a precise memory access or an imprecise memory access based upon a logical address value and method thereof | Daniel M. McCarthy, Joseph C. Circello, Richard Duerden, Gregory C. Edgington, Cliff L. Parrott | 1997-09-09 |
| 5485602 | Integrated circuit having a control signal for identifying coinciding active edges of two clock signals | Daniel M. McCarthy, James G. Gay | 1996-01-16 |
| 5477076 | Integrated circuit having an on chip thermal circuit requiring only one dedicated integrated circuit pin and method of operation | James G. Gay | 1995-12-19 |
| 5467455 | Data processing system and method for performing dynamic bus termination | James G. Gay | 1995-11-14 |
| 5376819 | Integrated circuit having an on chip thermal circuit requiring only one dedicated integrated circuit pin and method of operation | James G. Gay | 1994-12-27 |
| 5317701 | Method for refilling instruction queue by reading predetermined number of instruction words comprising one or more instructions and determining the actual number of instruction words used | Russell A. Reininger | 1994-05-31 |
| 5294845 | Data processor having an output terminal with selectable output impedances | Steven C. McMahan, Kenneth C. Scheuer, Michael G. Gallup, James G. Gay | 1994-03-15 |
| 5197144 | Data processor for reloading deferred pushes in a copy-back data cache | Robin W. Edenfield | 1993-03-23 |
| 5185694 | Data processing system utilizes block move instruction for burst transferring blocks of data entries where width of data blocks varies | Robin W. Edenfield, Ralph McGarity, Russell A. Reininger, Van B. Shahan | 1993-02-09 |
| 5162672 | Data processor having an output terminal with selectable output impedances | Steven C. McMahan, Kenneth C. Scheuer, Michael G. Gallup, James G. Gay | 1992-11-10 |
| 5155824 | System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address | Robin W. Edenfield, Russell A. Reininger | 1992-10-13 |
| 5127089 | Synchronous bus lock mechanism permitting bus arbiter to change bus master during a plurality of successive locked operand transfer sequences after completion of current sequence | James G. Gay | 1992-06-30 |
| 5119485 | Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation | Russell A. Reininger | 1992-06-02 |
| 5086407 | Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation | Ralph McGarity, Steven C. McMahan, Michael G. Gallup, Russell Stanphill, James G. Gay | 1992-02-04 |
| 5075846 | Memory access serialization as an MMU page attribute | Russell A. Reininger, Robin W. Edenfield, Van B. Shahan, Ralph McGarity, Eric Quintana | 1991-12-24 |
| 4666389 | Apparatus for forming compacts from solid particles | Matityahu Relis | 1987-05-19 |