| 10360162 |
Processing systems and methods for transitioning between privilege states based on an address of a next instruction to be fetched |
Joseph C. Circello, Kristen A. Hausman |
2019-07-23 |
| 10073797 |
Data processor device supporting selectable exceptions and method thereof |
Joseph C. Circello, Ujwala R. Malwade |
2018-09-11 |
| 10002076 |
Shared cache protocol for parallel search and replacement |
— |
2018-06-19 |
| 9824242 |
Programmable direct memory access channels |
Joseph C. Circello, John D. Mitchell, Peter J. Wilson, John J. Vaglica |
2017-11-21 |
| 9672164 |
Methods and systems for transitioning between a user state and a supervisor state based on a next instruction fetch address |
Joseph C. Circello, Kristen A. Hausman |
2017-06-06 |
| 9489316 |
Method and device implementing execute-only memory protection |
Joseph C. Circello, David J. Schimke |
2016-11-08 |
| 9201848 |
Floating point matrix multiplication co-processor |
— |
2015-12-01 |
| 9092647 |
Programmable direct memory access channels |
Joseph C. Circello, John D. Mitchell, Peter J. Wilson, John J. Vaglica |
2015-07-28 |
| 8417924 |
Data processing device and method of halting exception processing |
Joseph C. Circello, David J. Schimke |
2013-04-09 |
| 8312253 |
Data processor device having trace capabilities and method |
Joseph C. Circello, Sylvia M. Thirtle |
2012-11-13 |
| 7433803 |
Performance monitor with precise start-stop control |
Joseph C. Circello |
2008-10-07 |
| 6766433 |
System having user programmable addressing modes and method therefor |
Joseph C. Circello, Henri Cloetens, Nancy H. Woo, Bridget Catherine Hooser |
2004-07-20 |
| 5761215 |
Scan based path delay testing of integrated circuits containing embedded memory elements |
Paul William Hollis, Ruey J. Yu, Renny L. Eisele |
1998-06-02 |
| 5666509 |
Data processing system for performing either a precise memory access or an imprecise memory access based upon a logical address value and method thereof |
Joseph C. Circello, Richard Duerden, Gregory C. Edgington, Cliff L. Parrott, William B. Ledbetter, Jr. |
1997-09-09 |
| 5530804 |
Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes |
Gregory C. Edgington, Joseph C. Circello, Richard Duerden |
1996-06-25 |
| 5485602 |
Integrated circuit having a control signal for identifying coinciding active edges of two clock signals |
William B. Ledbetter, Jr., James G. Gay |
1996-01-16 |
| 5276836 |
Data processing device with common memory connecting mechanism |
Hiroaki Fukumaru, Siochi Takaya, Yoshihiro Miyazaki |
1994-01-04 |
| 5029070 |
Coherent cache structures and methods |
Joseph C. Circello, Gabriel R. Munguia, Nicholas J. Richardson |
1991-07-02 |
| 4928225 |
Coherent cache structures and methods |
Joseph C. Circello, Gabriel R. Munguia, Nicholas J. Richardson |
1990-05-22 |
| 4680702 |
Merge control apparatus for a store into cache of a data processing system |
— |
1987-07-14 |
