Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10978371 | Semiconductor device and method for manufacturing semiconductor device | Kenshi Kai, Rikihiro Maruyama | 2021-04-13 |
| 10661450 | Finger mechanism, robot hand and robot hand controlling method | Shota Okuyama, Yuya Wada | 2020-05-26 |
| 10398036 | Semiconductor device | Kenshi Kai, Rikihiro Maruyama | 2019-08-27 |
| 10286561 | Finger mechanism, robot hand and robot hand controlling method | Kanami Toui | 2019-05-14 |
| 6453391 | Multiplexed computer system | Yuuichiro Morita, Tetsuaki Nakamikawa, Shinichiro Yamaguchi, Naoto Miyazaki, Shin Kokura | 2002-09-17 |
| 6138248 | Common disk unit multi-computer system | Masahiko Saito, Hidehito Takewa, Kenichi Kurosawa, Shigenori Kaneko | 2000-10-24 |
| 6032265 | Fault-tolerant computer system | Hiroshi Oguro, Shinichiro Yamaguchi, Soichi Takaya, Masataka Hiramatsu, Nobuo Akeura | 2000-02-29 |
| 6003116 | Multiplexed computer system with the capability to copy data from one processor memory to another | Yuuichiro Morita, Tetsuaki Nakamikawa, Shinichiro Yamaguchi, Naoto Miyazaki, Shin Kokura | 1999-12-14 |
| 5852728 | Uninterruptible clock supply apparatus for fault tolerant computer system | Koji Matsuda, Soichi Takaya, Kenichi Kurosawa, Shinichiro Yamaguchi, Sako Ishikawa +3 more | 1998-12-22 |
| 5841963 | Dual information processing system having a plurality of data transfer channels | Tetsuaki Nakamikawa, Shin Kokura, Kenichi Kurosawa, Shinichiro Yamaguchi, Hiroshi Ohguro | 1998-11-24 |
| 5737513 | Method of and system for verifying operation concurrence in maintenance/replacement of twin CPUs | Koji Matsuda, Soichi Takaya, Kazuhiro Hyuga, Nobuo Akeura, Shinichiro Yamaguchi +2 more | 1998-04-07 |
| 5551007 | Method for controlling multiple common memories and multiple common memory system | Yoshiaki Takahashi, Manabu Araoka, Soichi Takaya, Hiroaki Fukumaru | 1996-08-27 |
| 5418404 | Data processing device and plug-in package | Manabu Araoka, Yoshiaki Takahashi, Atsushi Shikama, Tomoaki Nakamura, Masayuki Sakata | 1995-05-23 |
| 5345566 | Method and apparatus for controlling dual bus system | Masayuki Tanji, Hiroaki Fukumaru, Syoji Yamaguchi, Koji Masui, Hisao Ogawa | 1994-09-06 |
| 5343009 | Data processing device and plug-in package | Manabu Araoka, Yoshiaki Takahashi, Atsushi Shikama, Tomoaki Nakamura, Masayuki Sakata | 1994-08-30 |
| 5276836 | Data processing device with common memory connecting mechanism | Hiroaki Fukumaru, Siochi Takaya, Daniel M. McCarthy | 1994-01-04 |
| 5146569 | System for storing restart address of microprogram, determining the validity, and using valid restart address to resume execution upon removal of suspension | Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Morioka Takayuki +3 more | 1992-09-08 |
| 5029073 | Method for fast establishing a co-processor to memory linkage by main processor | Soichi Takaya | 1991-07-02 |
| 5003458 | Suspended instruction restart processing system based on a checkpoint microprogram address | Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Takayuki Morioka +3 more | 1991-03-26 |
| 4896258 | Data processor provided with instructions which refer to both tagged and tagless data | Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hiroaki Nakanishi, Kenzi Hirose +1 more | 1990-01-23 |
| 4841439 | Method for restarting execution interrupted due to page fault in a data processing system | Atsuhiko Nishikawa, Masayuki Tanji, Soichi Takaya, Shinichiro Yamaguchi | 1989-06-20 |
| 4807113 | Microprogrammed control data processing apparatus in which operand source and/or operand destination is determined independent of microprogram control | Hidekazu Matsumoto, Tadaaki Bandoh, Ryosei Hiraoka, Takayuki Morioka | 1989-02-21 |
| 4799056 | Display system having extended raster operation circuitry | Etsuo Hattori, Tomoyuki Iwami, Ryutaroh Ohbuchi | 1989-01-17 |
| 4783731 | Multicomputer system having dual common memories | Jushi Ide, Takeshi Kato, Hiroaki Nakanishi, Tadaaki Bandoh | 1988-11-08 |
| 4764869 | Method and apparatus for controlling interruption in the course of instruction execution in a processor | Soichi Takaya, Masayuki Tanji, Atsuhiko Nishikawa, Shinichiro Yamaguchi | 1988-08-16 |