Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6032265 | Fault-tolerant computer system | Hiroshi Oguro, Shinichiro Yamaguchi, Yoshihiro Miyazaki, Masataka Hiramatsu, Nobuo Akeura | 2000-02-29 |
| 5852728 | Uninterruptible clock supply apparatus for fault tolerant computer system | Koji Matsuda, Yoshihiro Miyazaki, Kenichi Kurosawa, Shinichiro Yamaguchi, Sako Ishikawa +3 more | 1998-12-22 |
| 5737513 | Method of and system for verifying operation concurrence in maintenance/replacement of twin CPUs | Koji Matsuda, Yoshihiro Miyazaki, Kazuhiro Hyuga, Nobuo Akeura, Shinichiro Yamaguchi +2 more | 1998-04-07 |
| 5551007 | Method for controlling multiple common memories and multiple common memory system | Yoshihiro Miyazaki, Yoshiaki Takahashi, Manabu Araoka, Hiroaki Fukumaru | 1996-08-27 |
| 5146569 | System for storing restart address of microprogram, determining the validity, and using valid restart address to resume execution upon removal of suspension | Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Morioka Takayuki +3 more | 1992-09-08 |
| 5029073 | Method for fast establishing a co-processor to memory linkage by main processor | Yoshihiro Miyazaki | 1991-07-02 |
| 5003458 | Suspended instruction restart processing system based on a checkpoint microprogram address | Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Takayuki Morioka +3 more | 1991-03-26 |
| 4967339 | Operation control apparatus for a processor having a plurality of arithmetic devices | Hiroaki Fukumaru, Takayuki Morioka, Tadaaki Bandoh, Shinichiro Yamaguchi, Kenji Hirose | 1990-10-30 |
| 4849876 | Address translation circuit including two translation buffers | Koji Ozawa, Manabu Araoka | 1989-07-18 |
| 4841439 | Method for restarting execution interrupted due to page fault in a data processing system | Atsuhiko Nishikawa, Yoshihiro Miyazaki, Masayuki Tanji, Shinichiro Yamaguchi | 1989-06-20 |
| 4764869 | Method and apparatus for controlling interruption in the course of instruction execution in a processor | Yoshihiro Miyazaki, Masayuki Tanji, Atsuhiko Nishikawa, Shinichiro Yamaguchi | 1988-08-16 |