Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6453391 | Multiplexed computer system | Yuuichiro Morita, Tetsuaki Nakamikawa, Naoto Miyazaki, Shin Kokura, Yoshihiro Miyazaki | 2002-09-17 |
| 6032265 | Fault-tolerant computer system | Hiroshi Oguro, Yoshihiro Miyazaki, Soichi Takaya, Masataka Hiramatsu, Nobuo Akeura | 2000-02-29 |
| 6003116 | Multiplexed computer system with the capability to copy data from one processor memory to another | Yuuichiro Morita, Tetsuaki Nakamikawa, Naoto Miyazaki, Shin Kokura, Yoshihiro Miyazaki | 1999-12-14 |
| 5852728 | Uninterruptible clock supply apparatus for fault tolerant computer system | Koji Matsuda, Soichi Takaya, Yoshihiro Miyazaki, Kenichi Kurosawa, Sako Ishikawa +3 more | 1998-12-22 |
| 5841963 | Dual information processing system having a plurality of data transfer channels | Tetsuaki Nakamikawa, Shin Kokura, Kenichi Kurosawa, Yoshihiro Miyazaki, Hiroshi Ohguro | 1998-11-24 |
| 5737513 | Method of and system for verifying operation concurrence in maintenance/replacement of twin CPUs | Koji Matsuda, Yoshihiro Miyazaki, Soichi Takaya, Kazuhiro Hyuga, Nobuo Akeura +2 more | 1998-04-07 |
| 5517669 | Cyclic data communication system | Yoshinori Ohkura, Takuji Hamada, Shunji Inada, Hiroshi Tomizawa | 1996-05-14 |
| 5146569 | System for storing restart address of microprogram, determining the validity, and using valid restart address to resume execution upon removal of suspension | Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Morioka Takayuki, Soichi Takaya +3 more | 1992-09-08 |
| 5003458 | Suspended instruction restart processing system based on a checkpoint microprogram address | Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Takayuki Morioka, Soichi Takaya +3 more | 1991-03-26 |
| 4967339 | Operation control apparatus for a processor having a plurality of arithmetic devices | Hiroaki Fukumaru, Soichi Takaya, Takayuki Morioka, Tadaaki Bandoh, Kenji Hirose | 1990-10-30 |
| 4896258 | Data processor provided with instructions which refer to both tagged and tagless data | Hidekazu Matsumoto, Tadaaki Bandoh, Hiroaki Nakanishi, Kenzi Hirose, Takao Kobayashi +1 more | 1990-01-23 |
| 4841439 | Method for restarting execution interrupted due to page fault in a data processing system | Atsuhiko Nishikawa, Yoshihiro Miyazaki, Masayuki Tanji, Soichi Takaya | 1989-06-20 |
| 4839846 | Apparatus for performing floating point arithmetic operations and rounding the result thereof | Kenji Hirose, Tadaaki Bandoh, Hidekazu Matsumoto, Hirokazu Hirayama, Hiroaki Nakanishi | 1989-06-13 |
| 4811269 | Bit slice multiplication circuit | Kenji Hirose, Tadaaki Bandoh, Hidekazu Matsumoto, Hirokazu Hirayama, Hiroaki Nakanishi | 1989-03-07 |
| 4764869 | Method and apparatus for controlling interruption in the course of instruction execution in a processor | Yoshihiro Miyazaki, Soichi Takaya, Masayuki Tanji, Atsuhiko Nishikawa | 1988-08-16 |