Issued Patents All Time
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7111187 | Information processor and information processing system utilizing interface for synchronizing clock signal | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 2006-09-19 |
| 6675311 | Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 2004-01-06 |
| 5974560 | Information processor and information processing system utilizing clock signal | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 1999-10-26 |
| 5968160 | Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory | Masahiko Saito, Kenichi Kurosawa, Yoshiki Kobayashi, Masahiro Iwamura, Takashi Hotta +3 more | 1999-10-19 |
| 5784630 | Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory | Masahiko Saito, Kenichi Kurosawa, Yoshiki Kobayashi, Masahiro Iwamura, Takashi Hotta +3 more | 1998-07-21 |
| 5640547 | Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 1997-06-17 |
| 5623626 | Logical cache memory for multi-processor system | Michio Morioka, Masayuki Tanji | 1997-04-22 |
| 5561775 | Parallel processing apparatus and method capable of processing plural instructions in parallel or successively | Kenichi Kurosawa, Shigeya Tanaka, Yasuhiro Nakatsuka | 1996-10-01 |
| 5542083 | Information processor and information processing system utilizing clock signal | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 1996-07-30 |
| 5506982 | Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 1996-04-09 |
| 5422980 | Inference processing method and apparatus | Kenichi Kurosawa, Masaru Shimada, Toshihiko Nakano, Toshihiro Hayashi | 1995-06-06 |
| 5404472 | Parallel processing apparatus and method capable of switching parallel and successive processing modes | Kenichi Kurosawa, Shigeya Tanaka, Yasuhiro Nakatsuka | 1995-04-04 |
| 5388249 | Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 1995-02-07 |
| 5297239 | Compile type knowledge processing tool, a high-speed inference method therefor and a system using the tool | Kenichi Kurosawa, Masaru Shimada, Hirokazu Hirayama, Kiyomi Mori | 1994-03-22 |
| 5287465 | Parallel processing apparatus and method capable of switching parallel and successive processing modes | Kenichi Kurosawa, Shigeya Tanaka, Yasuhiro Nakatsuka | 1994-02-15 |
| 5274829 | Information processing apparatus having micro instructions stored both in on-chip ROM and off-chip memory | Takashi Hotta, Yasuhiro Nakatsuka, Hideo Maejima | 1993-12-28 |
| 5247649 | Multi-processor system having a multi-port cache memory | — | 1993-09-21 |
| 5146569 | System for storing restart address of microprogram, determining the validity, and using valid restart address to resume execution upon removal of suspension | Shinichiro Yamaguchi, Hidekazu Matsumoto, Hirokazu Hirayama, Morioka Takayuki, Soichi Takaya +3 more | 1992-09-08 |
| 5133064 | Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 1992-07-21 |
| 5003458 | Suspended instruction restart processing system based on a checkpoint microprogram address | Shinichiro Yamaguchi, Hidekazu Matsumoto, Hirokazu Hirayama, Takayuki Morioka, Soichi Takaya +3 more | 1991-03-26 |
| 4975839 | Instruction decode method and arrangement suitable for a decoder of microprocessors | Yasuhiro Nakatsuka, Takashi Hotta, Yoshiki Fujioka | 1990-12-04 |
| 4967339 | Operation control apparatus for a processor having a plurality of arithmetic devices | Hiroaki Fukumaru, Soichi Takaya, Takayuki Morioka, Shinichiro Yamaguchi, Kenji Hirose | 1990-10-30 |
| 4896258 | Data processor provided with instructions which refer to both tagged and tagless data | Shinichiro Yamaguchi, Hidekazu Matsumoto, Hiroaki Nakanishi, Kenzi Hirose, Takao Kobayashi +1 more | 1990-01-23 |
| 4853890 | Vector processor | Shigeo Abe, Kotaro Hirasawa, Jushi Ide | 1989-08-01 |
| 4839846 | Apparatus for performing floating point arithmetic operations and rounding the result thereof | Kenji Hirose, Hidekazu Matsumoto, Shinichiro Yamaguchi, Hirokazu Hirayama, Hiroaki Nakanishi | 1989-06-13 |