Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8223017 | Control apparatus of showcase | Tetsuya Oketani, Masanobu Takeuchi, Yutaka Nishizaka | 2012-07-17 |
| 6216236 | Processing unit for a computer and a computer system incorporating such a processing unit | Takeshi Miyao, Manabu Araoka, Tomoaki Nakamura, Shigenori Kaneko, Koji Masui +6 more | 2001-04-10 |
| 5901281 | Processing unit for a computer and a computer system incorporating such a processing unit | Takeshi Miyao, Manabu Araoka, Tomoaki Nakamura, Shigenori Kaneko, Koji Masui +6 more | 1999-05-04 |
| 5651112 | Information processing system having performance measurement capabilities | Atsushi Matsuno, Masanori Naito, Hiroshi Kobayashi, Masanori Horie, Hideki Sato +2 more | 1997-07-22 |
| 5623626 | Logical cache memory for multi-processor system | Michio Morioka, Tadaaki Bandoh | 1997-04-22 |
| 5557753 | Information processing unit having a multiplexed bus and a bus control method therefor | Masashi Suenaga, Nobuo Tomita, Hiroshi Watanabe | 1996-09-17 |
| 5345566 | Method and apparatus for controlling dual bus system | Yoshihiro Miyazaki, Hiroaki Fukumaru, Syoji Yamaguchi, Koji Masui, Hisao Ogawa | 1994-09-06 |
| 5297290 | Method and apparatus for interruption processing in multi-processor system | Koji Masui | 1994-03-22 |
| 4841439 | Method for restarting execution interrupted due to page fault in a data processing system | Atsuhiko Nishikawa, Yoshihiro Miyazaki, Soichi Takaya, Shinichiro Yamaguchi | 1989-06-20 |
| 4764869 | Method and apparatus for controlling interruption in the course of instruction execution in a processor | Yoshihiro Miyazaki, Soichi Takaya, Atsuhiko Nishikawa, Shinichiro Yamaguchi | 1988-08-16 |