Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6751125 | Gate voltage reduction in a memory read | Erwin J. Prinz, Craig T. Swift, Jane A. Yater, Sung-Wei Lin | 2004-06-15 |
| 6444545 | Device structure for storing charge and method therefore | Michael A. Sadd, Sucharita Madhukar | 2002-09-03 |
| 6133093 | Method for forming an integrated circuit | Erwin J. Prinz, Gregory Munson Yeric, Kevin Yun-Kang Wu, Wei-Ming Chen | 2000-10-17 |
| 6101130 | Semiconductor device memory cell and method for selectively erasing the same | Juan Buxo, Danny Pak-Chum Shum, Thomas Jew | 2000-08-08 |
| 5741736 | Process for forming a transistor with a nonuniformly doped channel | Marius Orlowski | 1998-04-21 |
| 5739564 | Semiconductor device having a static-random-access memory cell | Yasunobu Kosa, Howard C. Kirsch, Thomas F. McNelly | 1998-04-14 |
| 5712501 | Graded-channel semiconductor device | Robert B. Davies, Jon J. Candelaria, Andreas Wild, Peter J. Zdebel | 1998-01-27 |
| 5661048 | Method of making an insulated gate semiconductor device | Robert B. Davies, Chandrasekhara Sudhama | 1997-08-26 |
| 5541132 | Insulated gate semiconductor device and method of manufacture | Robert B. Davies, Vida Ilderem, Mark Griswold, Diann Dow, James E. Prendergast +4 more | 1996-07-30 |
| 5536674 | Process for forming a static-random-access memory cell | Yasunobu Kosa, Howard C. Kirsch, Thomas F. McNelly | 1996-07-16 |
| 5485420 | Static-random-access memory cell and an integrated circuit having a static-random-access memory cell | Craig S. Lage, James D. Hayden, Kent J. Cooper | 1996-01-16 |
| 5377139 | Process forming an integrated circuit | Craig S. Lage, James D. Hayden, Kent J. Cooper | 1994-12-27 |
| 5275964 | Method for compactly laying out a pair of transistors | James D. Hayden | 1994-01-04 |
| 5243203 | Compact transistor pair layout and method thereof | James D. Hayden | 1993-09-07 |
| 5101257 | Semiconductor device having merged bipolar and MOS transistors and process for making the same | James D. Hayden, Thomas C. Mele | 1992-03-31 |
| 5082794 | Method of fabricating MOS transistors using selective polysilicon deposition | James R. Pfiester, Richard D. Sivan | 1992-01-21 |
| 5037777 | Method for forming a multi-layer semiconductor device using selective planarization | Thomas C. Mele, Wayne M. Paulson, Michael P. Woo | 1991-08-06 |
| 5024971 | Method for patterning submicron openings using an image reversal layer of material | James D. Hayden | 1991-06-18 |
| 4984042 | MOS transistors using selective polysilicon deposition | James R. Pfiester, Richard D. Sivan | 1991-01-08 |
| 4978626 | LDD transistor process having doping sensitive endpoint etching | Stephen S. Poon, James R. Pfiester, Jeffrey L. Klein | 1990-12-18 |
| 4852062 | EPROM device using asymmetrical transistor characteristics | James R. Pfiester, Charles Frederick Hart | 1989-07-25 |
| 4811066 | Compact multi-state ROM cell | James R. Pfiester | 1989-03-07 |
| 4801555 | Double-implant process for forming graded source/drain regions | Patrick J. Holly, Louis C. Parrillo | 1989-01-31 |