Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12205750 | 3D MIS-FO hybrid for embedded inductor package structure | Shih-Wen Tang, Che-Han Li | 2025-01-21 |
| 12100674 | Embedded resistor-capacitor film for fan out wafer level packaging | Ernesto Gutierrez, III, Shou-Cheng Hu | 2024-09-24 |
| 11621218 | Single side modular 3D stack up SiP with mold cavity | Shih-Wen Tang, Che-Han Li | 2023-04-04 |
| 11532489 | Pillared cavity down MIS-SiP | Ernesto Gutierrez, III, Eric Hu, Melvin Martin, Jerry Li, Francisco Vergara Cadacio | 2022-12-20 |
| 11309255 | Very thin embedded trace substrate-system in package (SIP) | Shou-Cheng Hu, Ian Kent, Ernesto Gutierrez, III, Melvin Martin, Rajesh Subraya Aiyandra | 2022-04-19 |
| 11251132 | Integrated type MIS substrate for thin double side SIP package | Chehan Jerry Li, Shou-Cheng Hu | 2022-02-15 |
| 11239185 | Embedded resistor-capacitor film for fan out wafer level packaging | Ernesto Gutierrez, III, Shou-Cheng Hu | 2022-02-01 |
| 11158551 | Modular WLCSP die daisy chain design for multiple die sizes | Duncan Barclay, Edward Horsburgh | 2021-10-26 |
| 11114359 | Wafer level chip scale package structure | Shou-Cheng Hu, Ian Kent, Ernesto Gutierrez, III, Jerry Li | 2021-09-07 |
| 11094669 | Wafer level molded PPGA (pad post grid array) for low cost package | Shou-Cheng Hu | 2021-08-17 |
| 11075167 | Pillared cavity down MIS-SIP | Ernesto Gutierrez, III, Eric Hu, Melvin Martin, Jerry Li, Francisco Vergara Cadacio | 2021-07-27 |
| 10727174 | Integrated circuit package and a method for forming a wafer level chip scale package (WLCSP) with through mold via (TMV) | Shou-Cheng Hu, Ernesto Gutierrez, III, Jerry Li | 2020-07-28 |
| 10636742 | Very thin embedded trace substrate-system in package (SIP) | Shou-Cheng Hu, Ian Kent, Ernesto Gutierrez, III, Melvin Martin, Rajesh Subraya Aiyandra | 2020-04-28 |
| 10629507 | System in package (SIP) | Che-Han Li, Ernesto Gutierrez, III, Shou-Cheng Hu | 2020-04-21 |
| 10083926 | Stress relief solutions on WLCSP large/bulk copper plane design | Ian Kent, Rajesh Subraya Aiyandra, Habeeb Mohiuddin Mohammed, Domingo Jr. Maggay, Robert Lamoon +1 more | 2018-09-25 |
| 7732242 | Composite board with semiconductor chips and plastic housing composition and method | Markus Brunnbauer, Edward Fuergut, Thorsten Meyer | 2010-06-08 |
| 7667333 | Stack of semiconductor chips | Laurence Singleton, Alexander Wollanke | 2010-02-23 |