Issued Patents All Time
Showing 51–75 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9947768 | Method for forming spacers for a transistor gate | — | 2018-04-17 |
| 9947541 | Method of forming spacers for a gate of a transistor | Olivier Pollet, Maxime Garcia-Barros | 2018-04-17 |
| 9934973 | Method for obtaining patterns in a layer | Stefan Landis, Sebastien Barnola, Thibaut David, Lamia Nouri | 2018-04-03 |
| 9853124 | Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers | Sylvain Barraud, Emmanuel Augendre, Sylvain Maitrejean | 2017-12-26 |
| 9805948 | Selective etching process of a mask disposed on a silicon substrate | — | 2017-10-31 |
| 9780191 | Method of forming spacers for a gate of a transistor | — | 2017-10-03 |
| 9780000 | Method for forming spacers for a transitor gate | Maxime Garcia-Barros | 2017-10-03 |
| 9773674 | Method for forming patterns by implanting | — | 2017-09-26 |
| 9698250 | Method for the surface etching of a three-dimensional structure | Christian Arvet, Sebastien Barnola | 2017-07-04 |
| 9679802 | Method of etching a porous dielectric material | — | 2017-06-13 |
| 9607840 | Method for forming spacers for a transistor gate | — | 2017-03-28 |
| 9607823 | Protection method for protecting a silicide layer | — | 2017-03-28 |
| 9583339 | Method for forming spacers for a transistor gate | Thibaut David, Olivier Joubert, Thorsten Lill, Srinivas D. Nemani, Laurent Vallier | 2017-02-28 |
| 9570317 | Microelectronic method for etching a layer | Olivier Joubert, Laurent Vallier | 2017-02-14 |
| 9543409 | Production of spacers at flanks of a transistor gate | Christian Arvet, Sebastien Barnola, Sebastien Lagrasta | 2017-01-10 |
| 9484217 | Method of forming contact openings for a transistor | — | 2016-11-01 |
| 9437418 | Method for forming spacers for a transistor gate | — | 2016-09-06 |
| 9378970 | Plasma etching process | Olivier Joubert, Gilles Cunge, Emilie Despiau-Pujo, Erwine Maude Pargon | 2016-06-28 |
| 9337350 | Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same | Laurent Grenouillet, Yannick Le Tiec, Maud Vinet | 2016-05-10 |
| 9257293 | Methods of forming silicon nitride spacers | Olivier Joubert, Thibaut David, Thorsten Lill | 2016-02-09 |
| 9076732 | Method to prepare semi-conductor device comprising a selective etching of a silicium—germanium layer | Yannick Le Tiec, Laurent Grenouillet, Maud Vinet | 2015-07-07 |
| 9070709 | Method for producing a field effect transistor with implantation through the spacers | Laurent Grenouillet, Yannick Le Tiec, Nicolas Loubet, Maud Vinet | 2015-06-30 |
| 9054045 | Method for isotropic etching | Gene Lee | 2015-06-09 |
| 9048011 | Method of obtaining patters in an antireflective layer | Olivier Joubert, Laurent Vallier | 2015-06-02 |
| 8994142 | Field effect transistor with offset counter-electrode contact | Maud Vinet, Laurent Grenouillet, Yannick Le Tiec | 2015-03-31 |