Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11888007 | Image sensor formed in sequential 3D technology | Lina Kadura, Perrine Batude, Christophe Licitra | 2024-01-30 |
| 11889704 | Device comprising wrap-gate transistors and method of manufacturing such a device | Sylvain Barraud | 2024-01-30 |
| 11810789 | Method of fabricating a semiconductor substrate having a stressed semiconductor region | Shay Reboh, Victor Boureau, Sylvain Maitrejean | 2023-11-07 |
| 11653506 | Resistive 3D memory | — | 2023-05-16 |
| 11631609 | Method for manufacturing a microelectronic device | Heimanu Niebojewski, Claire Fenouillet-Beranger | 2023-04-18 |
| 11532670 | 3D memory and manufacturing process | Sylvain Barraud | 2022-12-20 |
| 11139209 | 3D circuit provided with mesa isolation for the ground plane zone | Perrine Batude | 2021-10-05 |
| 11024544 | Assembly for 3D circuit with superposed transistor levels | Lamine Benaissa, Laurent Brunet | 2021-06-01 |
| 11011425 | Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer | Perrine Batude, Maud Vinet | 2021-05-18 |
| 10777680 | Integrated circuit chip with strained NMOS and PMOS transistors | Remy BERTHELON | 2020-09-15 |
| 10741565 | 3D SRAM circuit with double gate transistors with improved layout | Remy BERTHELON, Bastien Giraud | 2020-08-11 |
| 10651202 | 3D circuit transistors with flipped gate | Perrine Batude, Maud Vinet | 2020-05-12 |
| 10546929 | Optimized double-gate transistors and fabricating process | Remy BERTHELON | 2020-01-28 |
| 10504897 | Integrated circuit comprising balanced cells at the active | Remy BERTHELON | 2019-12-10 |
| 10446548 | Integrated circuit including balanced cells limiting an active area | Remy BERTHELON | 2019-10-15 |
| 10418486 | Integrated circuit chip with strained NMOS and PMOS transistors | Remy BERTHELON | 2019-09-17 |
| 10263110 | Method of forming strained MOS transistors | Remy BERTHELON, Didier Dutartre, Pierre Morin, Elise Baylac | 2019-04-16 |
| 9985029 | Integrated circuit with NMOS and PMOS transistors having different threshold voltages through channel doping and gate material work function schemes | — | 2018-05-29 |
| 9876032 | Method of manufacturing a device with MOS transistors | Sonarith Chhun, Emmanuel Josse, Gregory Bidal, Dominique Golanski, Jerome Mazurier +1 more | 2018-01-23 |
| 9558957 | Method for manufacturing a substrate provided with different active areas and with planar and three-dimensional transistors | Sebastien Barnola, Jerome Belledent | 2017-01-31 |
| 9520330 | Integrated circuit comprising PMOS transistors with different voltage thresholds | Nicolas Degors, Pierre Perreau | 2016-12-13 |
| 9514996 | Process for fabricating SOI transistors for an increased integration density | Denis Rideau | 2016-12-06 |
| 9214515 | Method for making a semiconductor structure with a buried ground plane | Yannick Le Tiec | 2015-12-15 |
| 9147750 | Process for fabricating a transistor comprising nanoscale semiconductor features using block copolymers | Simeon Morvan, Raluca Tiron | 2015-09-29 |
| 8853023 | Method for stressing a thin pattern and transistor fabrication method incorporating said method | Simeon Morvan, Jean-Charles Barbe | 2014-10-07 |