Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9876032 | Method of manufacturing a device with MOS transistors | Sonarith Chhun, Gregory Bidal, Dominique Golanski, Francois Andrieu, Jerome Mazurier +1 more | 2018-01-23 |
| 9735772 | Multi-orientation integrated cell, in particular input/output cell of an integrated circuit | Alexandre Dray | 2017-08-15 |
| 9543214 | Method of forming stressed semiconductor layer | Denis Rideau, Elise Baylac, Pierre Morin, Olivier Nier | 2017-01-10 |
| 9318372 | Method of stressing a semiconductor layer | Olivier Nier, Denis Rideau, Pierre Morin | 2016-04-19 |
| 9305828 | Method of forming stressed SOI layer | Denis Rideau, Olivier Nier | 2016-04-05 |
| 7504683 | Integrated electronic circuit incorporating a capacitor | Philippe Candelier, Thierry Devoivre, Sebastien Lefebvre | 2009-03-17 |
| 7078764 | Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and integrated circuit including this kind of transistor | Thomas Skotnicki | 2006-07-18 |
| 6861684 | Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor | Thomas Skotnicki | 2005-03-01 |
| 6746923 | Method of fabricating a vertical quadruple conduction channel insulated gate transistor | Thomas Skotnicki | 2004-06-08 |