Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12211754 | Semiconductor chip manufacturing method | Pierpaolo Monge Roffarello, Isabella MICA, Alexandra Abbadie | 2025-01-28 |
| 11978710 | Integrated circuit comprising a substrate equipped with a trap-rich region, and fabricating process | — | 2024-05-07 |
| 11757054 | Integrated optical sensor with pinned photodiodes | — | 2023-09-12 |
| 11562927 | Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure | Jean-Pierre Carrere, Jean-Luc Huguenin, Clement Pribat, Sarah Kuster | 2023-01-24 |
| 11075177 | Integrated circuit comprising a substrate equipped with a trap-rich region, and fabricating process | — | 2021-07-27 |
| 10978340 | Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure | Jean-Pierre Carrere, Jean-Luc Huguenin, Clement Pribat, Sarah Kuster | 2021-04-13 |
| 10658578 | Memory cell comprising a phase-change material | Pierre Morin | 2020-05-19 |
| 10535552 | Method for manufacture of a semiconductor wafer suitable for the manufacture of an SOI substrate, and SOI substrate wafer thus obtained | Herve Jaouen | 2020-01-14 |
| 10263110 | Method of forming strained MOS transistors | Remy BERTHELON, Pierre Morin, Francois Andrieu, Elise Baylac | 2019-04-16 |
| 10262898 | Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure | Jean-Pierre Carrere, Jean-Luc Huguenin, Clement Pribat, Sarah Kuster | 2019-04-16 |
| 9929039 | Method for manufacture of a semiconductor wafer suitable for the manufacture of an SOI substrate, and SOI substrate wafer thus obtained | Herve Jaouen | 2018-03-27 |
| 9759546 | Method for measuring thickness variations in a layer of a multilayer semiconductor structure | Oleg Kononchuk | 2017-09-12 |
| 9711550 | Pinned photodiode with a low dark current | Laurent Favennec, Francois Roy | 2017-07-18 |
| 9704903 | Front-side imager having a reduced dark current on SOI substrate | — | 2017-07-11 |
| 9312408 | Imager having a reduced dark current through an increased bulk doping level | — | 2016-04-12 |
| 8975730 | Method for protection of a layer of a vertical stack and corresponding device | Michel Marty, Sebastien Jouan | 2015-03-10 |
| 8975154 | Process for producing at least one deep trench isolation | Zahra Aitfqirali-Guerry, Yves Campidelli, Denis Pellissier-Tanon | 2015-03-10 |
| 8603887 | Method for depositing a silicon oxide layer of same thickness on silicon and on silicon-germanium | Nicolas L. Breil, Yves Campidelli, Olivier Gourhant | 2013-12-10 |
| 8524522 | Microelectronic device, in particular back side illuminated image sensor, and production process | Michel Marty, Francois Roy, Pascal Besson, Jens Prima | 2013-09-03 |
| 8168536 | Realization of self-positioned contacts by epitaxy | Philippe Coronel, Nicolas Loubet | 2012-05-01 |
| 8158495 | Process for forming a silicon-based single-crystal portion | Laurent Rubaldo, Alexandre Talbot | 2012-04-17 |
| 7906381 | Method for integrating silicon-on-nothing devices with standard CMOS devices | Nicolas Loubet, Stephane Monfray | 2011-03-15 |
| 7892927 | Transistor with a channel comprising germanium | Stephane Monfray, Thomas Skotnicki, Alexandre Talbot | 2011-02-22 |
| 7776745 | Method for etching silicon-germanium in the presence of silicon | Nicolas Loubet, Alexandre Talbot, Laurent Rubaldo | 2010-08-17 |
| 7776679 | Method for forming silicon wells of different crystallographic orientations | Nicolas Loubet, Frederic Boeuf | 2010-08-17 |