Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6417056 | Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge | Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung +2 more | 2002-07-09 |
| 6417054 | Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide | Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2002-07-09 |
| 6406945 | Method for forming a transistor gate dielectric with high-K and low-K regions | James Yong Meng Lee, Ying-Keung Leung, Jia Zhen Zheng, Lap Chan, Elgin Quek +2 more | 2002-06-18 |
| 6403485 | Method to form a low parasitic capacitance pseudo-SOI CMOS device | Elgin Quek, Ravi Sundaresan, Yang Pan, James Lee Yong Meng, Ying Keung +2 more | 2002-06-11 |
| 6399448 | Method for forming dual gate oxide | Madhusudan Mukhopadhyay, Chivukula Subrahmanyam | 2002-06-04 |
| 6387765 | Method for forming an extended metal gate using a damascene process | Vijai Kumar Chhagan, Mei Sheng Zhou, Henry Gerung, Simon Chooi | 2002-05-14 |
| 6380088 | Method to form a recessed source drain on a trench side wall with a replacement gate technique | Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2002-04-30 |
| 6355581 | Gas-phase additives for an enhancement of lateral etch component during high density plasma film deposition to improve film gap-fill capability | Vladislav Vassiliev, John Sudijono, Jie Yu | 2002-03-12 |
| 6346468 | Method for forming an L-shaped spacer using a disposable polysilicon spacer | Subhash Gupta, Vijai Chhagan | 2002-02-12 |
| 6337262 | Self aligned T-top gate process integration | Chivukula Subrahmanyam, Vijai Kumar Chhagan, Henry Gerung | 2002-01-08 |
| 6316304 | Method of forming spacers of multiple widths | Jie Yu, Tjin Tjin Tjoa, Kelvin Wei Loong Loh | 2001-11-13 |
| 6312999 | Method for forming PLDD structure with minimized lateral dopant diffusion | Subrahamanyam Chivukula, Madhusudan Mukhopdhyay, Palanivel Balasubramaniam | 2001-11-06 |
| 6313008 | Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon | Ying-Keung Leung, Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan +2 more | 2001-11-06 |
| 6306714 | Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide | Yang Pan, James Yongmeng Lee, Ying-Keung Leung, Jia Zhen Zheng, Lap Chan +2 more | 2001-10-23 |
| 6306715 | Method to form smaller channel with CMOS device by isotropic etching of the gate materials | Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2001-10-23 |
| 6303449 | Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP | Yang Pan, James Yong Meng Lee, Ying-Keung Leung, Jia Zhen Zheng, Lap Chan +2 more | 2001-10-16 |
| 6303447 | Method for forming an extended metal gate using a damascene process | Vijai Chhagan, Mei Sheng Zhou, Henry Gerung, Simon Chooi | 2001-10-16 |
| 6300177 | Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials | Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung, Jia Zhen Zheng +2 more | 2001-10-09 |
| 6300251 | Repeatable end point method for anisotropic etch of inorganic buried anti-reflective coating layer over silicon | Vijakomar Chhagan, Henry Gerung | 2001-10-09 |
| 6294480 | Method for forming an L-shaped spacer with a disposable organic top coating | Jie Yu, Minghui Fan, Chiew Wah Yap | 2001-09-25 |
| 6284613 | Method for forming a T-gate for better salicidation | Chivukula Subrahmanyam, Ramakrishnan Rajagopal | 2001-09-04 |
| 6281093 | Method to reduce trench cone formation in the fabrication of shallow trench isolations | Qinghua Zhong, Zheng Zou, Henry Gerung | 2001-08-28 |
| 6277716 | Method of reduce gate oxide damage by using a multi-step etch process with a predictable premature endpoint system | Vijaikumar Chhagan, Tjin Tjin Tjoa | 2001-08-21 |
| 6277683 | Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer | Henry Gerung, Jie Yu, Pei Ching Lee | 2001-08-21 |
| 6277700 | High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness | Jie Yu, Guan Ping Wu | 2001-08-21 |