Issued Patents All Time
Showing 76–100 of 129 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6505260 | Computer system with adaptive memory arbitration scheme | Kenneth T. Chin, C. Kevin Coffee, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +2 more | 2003-01-07 |
| 6356972 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Kenneth T. Chin, Clarence K. Coffee, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2002-03-12 |
| 6286083 | Computer system with adaptive memory arbitration scheme | Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo +2 more | 2001-09-04 |
| 6279065 | Computer system with improved memory access | Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo +1 more | 2001-08-21 |
| 6275885 | System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache | Kenneth T. Chin, John E. Larson, Robert A. Lester | 2001-08-14 |
| 6272651 | System and method for improving processor read latency in a system employing error checking and correction | Kenneth T. Chin, Clarence K. Coffee, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-08-07 |
| 6249847 | Computer system with synchronous memory arbiter that permits asynchronous memory requests | Kenneth T. Chin, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo | 2001-06-19 |
| 6247102 | Computer system employing memory controller and bridge interface permitting concurrent operation | Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo +3 more | 2001-06-12 |
| 6227041 | Method and apparatus for measuring volatile content | William Edward Jennings | 2001-05-08 |
| 6216190 | System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus | Kenneth T. Chin, Clarence K. Coffee, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-04-10 |
| 6209067 | Computer system controller and method with processor write posting hold off on PCI master memory request | Michael Moriarty, John E. Larson, Jens K. Ramsey | 2001-03-27 |
| 6209052 | System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter | Kenneth T. Chin, Clarence K. Coffee, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-03-27 |
| 6202101 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Kenneth T. Chin, Clarence K. Coffee, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-03-13 |
| 6199118 | System and method for aligning an initial cache line of data read from an input/output device by a central processing unit | Kenneth T. Chin, Clarence K. Coffee, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-03-06 |
| 6160562 | System and method for aligning an initial cache line of data read from local memory by an input/output device | Kenneth T. Chin, Clarence K. Coffee, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2000-12-12 |
| 6115791 | Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control | Gary W. Thome | 2000-09-05 |
| 6055495 | Speech segmentation | Roger Cecil Ferry Tucker | 2000-04-25 |
| 5949436 | Accelerated graphics port multiple entry gart cache allocation system and method | Ronald T. Horan, Phillip M. Jones, Gregory N. Santos, Robert A. Lester, Jerome J. Johnson | 1999-09-07 |
| 5938739 | Memory controller including write posting queues, bus read control logic, and a data contents counter | Gary W. Thome, Michael Moriarty, Jens K. Ramsey, John E. Larson | 1999-08-17 |
| 5848428 | Sense amplifier decoding in a memory device to reduce power consumption | — | 1998-12-08 |
| 5835948 | Single bank, multiple way cache memory | Sompong Paul Olarig, Jens K. Ramsey | 1998-11-10 |
| 5819105 | System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device | Michael Moriarty, John E. Larson, Gary W. Thome | 1998-10-06 |
| 5809549 | Burst SRAMs for use with a high speed clock | Gary W. Thome | 1998-09-15 |
| 5796992 | Circuit for switching between synchronous and asynchronous memory refresh cycles in low power mode | James R. Reif, Todd Deschepper | 1998-08-18 |
| 5793693 | Cache memory using unique burst counter circuitry and asynchronous interleaved RAM banks for zero wait state operation | Jeffrey C. Stevens, Guy E. McSwain | 1998-08-11 |