Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11922505 | Trade asset card | Rameshchandra Bhaskar Ketharaju, Prabal Nandi, Shanmukeswara Rao Donkada | 2024-03-05 |
| 11605126 | Detecting fraud in credit applications | Jie Chen, Carmel Nadav | 2023-03-14 |
| 11599579 | Anomaly visualization for computerized models | Carmel Nadav, Connor Jennings, Mahima Rawat | 2023-03-07 |
| 11508009 | Trade asset card | Rameshchandra Bhaskar Ketharaju, Prabal Nandi, Shanmukeswara Rao Donkada | 2022-11-22 |
| 11501048 | Estimating hardness of formal properties using on-the-fly machine learning | Arunava Saha, Chuan Jiang | 2022-11-15 |
| 11074302 | Anomaly visualization for computerized models | Carmel Nadav, Connor Jennings, Mahima Rawat | 2021-07-27 |
| 10521536 | RTL verification using computational complexity-based property ranking and scheduling | Jinqing Yu, Ming-Ying Chung, Arunava Saha | 2019-12-31 |
| 10503853 | Formal verification using cached search path information to verify previously proved/disproved properties | Arunava Saha, Himanshu Jain, Ashvin M. Dsouza, Per M. Bjesse | 2019-12-10 |
| 10140403 | Managing model checks of sequential designs | Jinqing Yu | 2018-11-27 |
| 9430595 | Managing model checks of sequential designs | Jinqing Yu | 2016-08-30 |
| 8627249 | Method and system for generating design constraints | Marcalo Glusman, Angela Krstic, Yee-Wing Hsieh, Andy Lai Lin | 2014-01-07 |
| RE44479 | Method and mechanism for implementing electronic designs having power information specifications background | Qi Wang, Ankur Gupta, Pinhong Chen, Christina Chu, Huan-Chih Tsai +6 more | 2013-09-03 |
| 8516422 | Method and mechanism for implementing electronic designs having power information specifications background | Qi Wang, Ankur Gupta, Pinhong Chen, Christina Chu, Huan-Chih Tsai +5 more | 2013-08-20 |
| 8442111 | Optimal power usage in encoding data streams | Shashank Garg, Vinayak Pore, Soumenkumar Dey, Harikrishna Madadi Reddy, Manindra Parhy | 2013-05-14 |
| 8209648 | Verifying multiple constraints for circuit designs | Shan-Chyun Ku, Marcelo Glusman, Yee-Wing Hsieh, Angela Krstic, Sarath Kirihennedige | 2012-06-26 |
| 7962886 | Method and system for generating design constraints | Marcelo Glusman, Angela Krstic, Yee-Wing Hsieh, Andy Lai Lin | 2011-06-14 |
| 7739629 | Method and mechanism for implementing electronic designs having power information specifications background | Qi Wang, Ankur Gupta, Pinhong Chen, Christina Chu, Huan-Chih Tsai +5 more | 2010-06-15 |
| 7694251 | Method and system for verifying power specifications of a low power design | Bharat Chandramouli, Huan-Chih Tsai, Chih-Chang Lin, Madan M. Das | 2010-04-06 |
| 7669165 | Method and system for equivalence checking of a low power design | Rajat Arora, Chih-Chang Lin, Huan-Chih Tsai, Bharat Chandramouli, Kei-Yong Khoo | 2010-02-23 |
| 7644380 | Method for analyzing circuits having MOS devices | Samuel L. Kerner, Chih-Chang Lin | 2010-01-05 |
| 7620919 | Method and system for logic equivalence checking | Yung-Te Lai, Bret Siarowski, Kei-Yong Khoo, Chih-Chang Lin | 2009-11-17 |
| 7620918 | Method and system for logic equivalence checking | Yung-Te Lai, Bret Siarowski, Kei-Yong Khoo, Chih-Chang Lin | 2009-11-17 |
| 7587690 | Method and system for global coverage analysis | Bret Siarkowski | 2009-09-08 |
| 7266790 | Method and system for logic equivalence checking | Yung-Te Lai, Bret Siarkowski, Kei-Yong Khoo, Chih-Chang Lin | 2007-09-04 |
| 6848084 | Method and apparatus for verification of memories at multiple abstraction levels | Mitchell Hines, Chih-Chang Lin | 2005-01-25 |