SK

Sarath Kirihennedige

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 Fremont, CA: #6,509 of 9,298 inventorsTop 75%
🗺 California: #247,236 of 386,348 inventorsTop 65%
Overall (All Time): #3,212,867 of 4,157,543Top 80%
1
Patents All Time

Issued Patents All Time

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
8209648 Verifying multiple constraints for circuit designs Shan-Chyun Ku, Marcelo Glusman, Yee-Wing Hsieh, Manish Pandey, Angela Krstic 2012-06-26