MG

Marcelo Glusman

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
IN Intel: 1 patents #18,218 of 30,777Top 60%
📍 Holon, CA: #15 of 16 inventorsTop 95%
Overall (All Time): #1,553,563 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
8209648 Verifying multiple constraints for circuit designs Shan-Chyun Ku, Yee-Wing Hsieh, Manish Pandey, Angela Krstic, Sarath Kirihennedige 2012-06-26
7962886 Method and system for generating design constraints Manish Pandey, Angela Krstic, Yee-Wing Hsieh, Andy Lai Lin 2011-06-14
7203631 System and method to analyze VLSI designs Ranan Fraer, Osnat Weissberg, Amitai Irron, Gila Kamhi, Sela Mador-Haim +1 more 2007-04-10