SK

Shan-Chyun Ku

FT Faraday Technology: 2 patents #110 of 417Top 30%
CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
Overall (All Time): #1,553,564 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
8209648 Verifying multiple constraints for circuit designs Marcelo Glusman, Yee-Wing Hsieh, Manish Pandey, Angela Krstic, Sarath Kirihennedige 2012-06-26
7240082 Method for processing efficiency in a pipeline architecture 2007-07-03
6944749 Method for quickly determining length of an execution package 2005-09-13