BS

Bret Siarowski

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
📍 Marlborough, MA: #391 of 796 inventorsTop 50%
🗺 Massachusetts: #42,150 of 88,656 inventorsTop 50%
Overall (All Time): #2,140,678 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
7620918 Method and system for logic equivalence checking Manish Pandey, Yung-Te Lai, Kei-Yong Khoo, Chih-Chang Lin 2009-11-17
7620919 Method and system for logic equivalence checking Manish Pandey, Yung-Te Lai, Kei-Yong Khoo, Chih-Chang Lin 2009-11-17