YL

Yung-Te Lai

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
📍 Cupertino, CA: #2,327 of 6,989 inventorsTop 35%
🗺 California: #93,399 of 386,348 inventorsTop 25%
Overall (All Time): #869,220 of 4,157,543Top 25%
6
Patents All Time

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
7823104 Determination of single-fix rectification function Cheng-Ta Hsieh, Yifeng Wang, Chih-Chang Lin 2010-10-26
7620918 Method and system for logic equivalence checking Manish Pandey, Bret Siarowski, Kei-Yong Khoo, Chih-Chang Lin 2009-11-17
7620919 Method and system for logic equivalence checking Manish Pandey, Bret Siarowski, Kei-Yong Khoo, Chih-Chang Lin 2009-11-17
7266790 Method and system for logic equivalence checking Manish Pandey, Bret Siarkowski, Kei-Yong Khoo, Chih-Chang Lin 2007-09-04
7240311 Combinational equivalence checking methods and systems with internal don't cares Chioumin M. Chang, Kung-Chien Chen, Chih-Chang Lin 2007-07-03
6842884 Combinational equivalence checking methods and systems with internal don't cares Chioumin M. Chang, Kung-Chien Chen, Chih-Chang Lin 2005-01-11