BC

Bharat Chandramouli

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
Microsoft: 1 patents #24,826 of 40,388Top 65%
📍 San Jose, CA: #14,517 of 32,062 inventorsTop 50%
🗺 California: #149,087 of 386,348 inventorsTop 40%
Overall (All Time): #1,385,953 of 4,157,543Top 35%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
11573961 Delta graph traversing system Yuqing Gao, Derek Paul Baron 2023-02-07
7694251 Method and system for verifying power specifications of a low power design Huan-Chih Tsai, Manish Pandey, Chih-Chang Lin, Madan M. Das 2010-04-06
7669165 Method and system for equivalence checking of a low power design Manish Pandey, Rajat Arora, Chih-Chang Lin, Huan-Chih Tsai, Kei-Yong Khoo 2010-02-23