Issued Patents All Time
Showing 51–69 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8580332 | Thin-film battery methods for complexity reduction | Nety M. Krishna | 2013-11-12 |
| 8568571 | Thin film batteries and methods for manufacturing same | Michael W. Stowell, Nety M. Krishna | 2013-10-29 |
| 8464419 | Methods of and factories for thin-film battery manufacturing | Stefan Bangert, Dieter Haas, Omkaram Nalamasu | 2013-06-18 |
| 8218224 | Laminated electrically tintable windows | Dieter Haas, Stefan Bangert, Nety M. Krishna, Winfried Hoffmann | 2012-07-10 |
| 8168265 | Method for manufacturing electrochromic devices | Nety M. Krishna | 2012-05-01 |
| 8168318 | Method for high volume manufacturing of thin film batteries | Nety M. Krishna, Kurt Eisenbeiser, William J. Dauksher, Jon J. Candelaria | 2012-05-01 |
| 8083859 | Arrangement and method for removing alkali- or alkaline earth-metals from a vacuum coating chamber | Stefan Bangert, Jose Manuel DIEGUEZ-CAMPO, Michael Koenig, Nety M. Krishna | 2011-12-27 |
| 7915122 | Self-aligned cell integration scheme | Richard J. Carter, Hemanshu Bhatt, Shiqun Gu, Peter A. Burke, James R. B. Elmer +2 more | 2011-03-29 |
| 7710671 | Laminated electrically tintable windows | Dieter Haas, Stefan Bangert, Nety M. Krishna, Winfried Hoffmann | 2010-05-04 |
| 7675177 | Forming copper interconnects with Sn coatings | Hongqiang Lu, Wilbur G. Catabay | 2010-03-09 |
| 7582566 | Method for redirecting void diffusion away from vias in an integrated circuit design | Derryl D. J. Allman, Hemanshu Bhatt, Charles E. May, Peter A. Burke, Sey-Shing Sun +2 more | 2009-09-01 |
| 7436040 | Method and apparatus for diverting void diffusion in integrated circuit conductors | Derryl D. J. Allman, Hemanshu Bhatt, Charles E. May, Peter A. Burke, Sey-Shing Sun +2 more | 2008-10-14 |
| 7361965 | Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design | Derryl D. J. Allman, Hemanshu Bhatt, Charles E. May, Peter A. Burke, Sey-Shing Sun +2 more | 2008-04-22 |
| 7300869 | Integrated barrier and seed layer for copper interconnect technology | Sey-Shing Sun, Peter A. Burke | 2007-11-27 |
| 7204920 | Contact ring design for reducing bubble and electrolyte effects during electrochemical plating in manufacturing | Gregory Piatt, Hiroshi Mizuno | 2007-04-17 |
| 7179736 | Method for fabricating planar semiconductor wafers | Peter A. Burke, Sey-Shing Sun | 2007-02-20 |
| 6884720 | Forming copper interconnects with Sn coatings | Hongqiang Lu, Wilbur G. Catabay | 2005-04-26 |
| 6838379 | PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER | Jayanthi Pallinti, William K. Barth | 2005-01-04 |
| 6808612 | Method and apparatus to overcome anomalies in copper seed layers and to tune for feature size and aspect ratio | Peter Hey | 2004-10-26 |