Issued Patents All Time
Showing 26–33 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9753733 | Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer | Conrado Blasco-Allue | 2017-09-05 |
| 9632791 | Cache for patterns of instructions with multiple forward control transfers | Muawya M. Al-Otoom, Ronald P. Hall, Michael L. Karm | 2017-04-25 |
| 9626185 | IT instruction pre-decode | Shyam Sundar, Conrado Blasco-Allue, Gerard R. Williams, III, Wei-Han Lien, Ramesh Gunna | 2017-04-18 |
| 9557999 | Loop buffer learning | Conrado Blasco-Allue | 2017-01-31 |
| 9524011 | Instruction loop buffer with tiered power savings | Ronald P. Hall, Michael L. Karm, David Williamson | 2016-12-20 |
| 9471322 | Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold | Conrado Blasco | 2016-10-18 |
| 9201658 | Branch predictor for wide issue, arbitrarily aligned fetch that can cross cache line boundaries | Gerard R. Williams, III, James B. Keller | 2015-12-01 |
| 8914580 | Reducing cache power consumption for sequential accesses | Rajat Goel | 2014-12-16 |