Issued Patents All Time
Showing 26–50 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7202698 | Integrated circuit having a programmable input structure with bounce capability | Steven P. Young | 2007-04-10 |
| 7196543 | Integrated circuit having a programmable input structure with optional fanout capability | Steven P. Young | 2007-03-27 |
| 7057413 | Large crossbar switch implemented in FPGA | Steven P. Young, Peter H. Alfke, Colm P. Fewer | 2006-06-06 |
| 6956399 | High-speed lookup table circuits and methods for programmable logic devices | — | 2005-10-18 |
| 6933747 | Structures and methods of testing interconnect structures in programmable logic devices | Steven P. Young, Ramakrishna K. Tanikella | 2005-08-23 |
| 6907595 | Partial reconfiguration of a programmable logic device using an on-chip processor | Derek R. Curd, Punit S. Kalra, Richard J. LeBlanc, Vincent P. Eck, Stephen W. Trynosky +1 more | 2005-06-14 |
| 6864715 | Windowing circuit for aligning data and clock signals | Steven P. Young, Christopher D. Ebeling, Jason R. Bergendahl, Arthur J. Behiel | 2005-03-08 |
| 6798241 | Methods for aligning data and clock signals | Steven P. Young, Christopher D. Ebeling, Jason R. Bergendahl, Arthur J. Behiel | 2004-09-28 |
| 6798270 | Pass gate multiplexer circuit with reduced susceptibility to single event upsets | — | 2004-09-28 |
| 6759869 | Large crossbar switch implemented in FPGA | Steven P. Young, Peter H. Alfke, Colm P. Fewer | 2004-07-06 |
| 6670826 | Configurable logic block with a storage element clocked by a write strobe pulse | — | 2003-12-30 |
| 6671202 | Programmable circuit structures with reduced susceptibility to single event upsets | — | 2003-12-30 |
| 6621296 | FPGA lookup table with high speed read decorder | Richard A. Carberry, Steven P. Young | 2003-09-16 |
| 6617912 | Pass gate multiplexer circuit with reduced susceptibility to single event upsets | — | 2003-09-09 |
| 6529040 | FPGA lookup table with speed read decoder | Richard A. Carberry, Steven P. Young | 2003-03-04 |
| 6526557 | Architecture and method for partially reconfiguring an FPGA | Steven P. Young | 2003-02-25 |
| 6448808 | Interconnect structure for a programmable logic device | Steven P. Young, Kamal Chaudhary | 2002-09-10 |
| 6445209 | FPGA lookup table with NOR gate write decoder and high speed read decoder | Steven P. Young, Richard A. Carberry | 2002-09-03 |
| 6373279 | FPGA lookup table with dual ended writes for ram and shift register modes | Steven P. Young, Richard A. Carberry | 2002-04-16 |
| 6362648 | Multiplexer for implementing logic functions in a programmable logic device | Bernard J. New, Steven P. Young, Shekhar Bapat, Kamal Chaudhary, Roman Iwanczuk | 2002-03-26 |
| 6346825 | Block RAM with configurable data width and parity for use in a field programmable gate array | Raymond C. Pang, Steven P. Young | 2002-02-12 |
| 6323682 | FPGA architecture with wide function multiplexers | Steven P. Young | 2001-11-27 |
| 6297665 | FPGA architecture with dual-port deep look-up table RAMS | Steven P. Young | 2001-10-02 |
| 6292022 | Interconnect structure for a programmable logic device | Steven P. Young, Kamal Chaudhary | 2001-09-18 |
| 6288568 | FPGA architecture with deep look-up table RAMs | Steven P. Young | 2001-09-11 |