Issued Patents All Time
Showing 51–73 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6282127 | Block RAM with reset to user selected value | Raymond C. Pang, Steven P. Young | 2001-08-28 |
| 6262597 | FIFO in FPGA having logic elements that include cascadable shift registers | Bruce A. Newgard, William E. Allaire, Steven P. Young | 2001-07-17 |
| 6232845 | Circuit for measuring signal delays in synchronous memory elements | Christopher H. Kingsley, Robert W. Wells, Robert D. Patrie | 2001-05-15 |
| 6204689 | Input/output interconnect circuit for FPGAs | Andrew K. Percey, Steven P. Young | 2001-03-20 |
| 6204690 | FPGA architecture with offset interconnect lines | Steven P. Young, Kamal Chaudhary | 2001-03-20 |
| 6201410 | Wide logic gate implemented in an FPGA configurable logic element | Bernard J. New, Steven P. Young, Shekhar Bapat, Kamal Chaudhary, Roman Iwanczuk | 2001-03-13 |
| 6124731 | Configurable logic element with ability to evaluate wide logic functions | Steven P. Young, Shekhar Bapat, Kamal Chaudhary, Roman Iwanczuk | 2000-09-26 |
| 6118298 | Structure for optionally cascading shift registers | Bruce A. Newgard, William E. Allaire, Steven P. Young | 2000-09-12 |
| 6107826 | Interconnect structure for FPGA with configurable delay locked loop | Steven P. Young | 2000-08-22 |
| 6107827 | FPGA CLE with two independent carry chains | Steven P. Young, Bernard J. New, Nicolas John Camilleri, Shekhar Bapat, Kamal Chaudhary +1 more | 2000-08-22 |
| 6101132 | Block RAM with reset | F. Erich Goetting | 2000-08-08 |
| 6072348 | Programmable power reduction in a clock-distribution circuit | Bernard J. New, Steven P. Young | 2000-06-06 |
| 6051992 | Configurable logic element with ability to evaluate five and six input functions | Steven P. Young, Shekhar Bapat, Kamal Chaudhary, Roman Iwanczuk | 2000-04-18 |
| 5963050 | Configurable logic element with fast feedback paths | Steven P. Young, Bernard J. New, Nicolas John Camilleri, Shekhar Bapat, Kamal Chaudhary +1 more | 1999-10-05 |
| 5942913 | FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines | Steven P. Young, Kamal Chaudhary, Sridhar Krishnamurthy | 1999-08-24 |
| 5920202 | Configurable logic element with ability to evaluate five and six input functions | Steven P. Young, Shekhar Bapat, Kamal Chaudhary, Roman Iwanczuk | 1999-07-06 |
| 5914616 | FPGA repeatable interconnect structure with hierarchical interconnect lines | Steven P. Young, Kamal Chaudhary | 1999-06-22 |
| 5907248 | FPGA interconnect structure with high-speed high fanout capability | Steven P. Young | 1999-05-25 |
| 5889413 | Lookup tables which double as shift registers | — | 1999-03-30 |
| 5844844 | FPGA memory element programmably triggered on both clock edges | Stephen M. Trimberger, Steven P. Young | 1998-12-01 |
| 5787007 | Structure and method for loading RAM data within a programmable logic device | — | 1998-07-28 |
| 5724276 | Logic block structure optimized for sum generation | Jonathan Rose | 1998-03-03 |
| 5627480 | Tristatable bidirectional buffer for tristate bus lines | Steven P. Young | 1997-05-06 |