Issued Patents All Time
Showing 51–75 of 91 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6937518 | Programming of a flash memory cell | Sheung-Hee Park, Wing Leung | 2005-08-30 |
| 6911704 | Memory cell array with staggered local inter-connect structure | Mark Randolph, Sameer Haddad, Timothy Thurgate | 2005-06-28 |
| 6897518 | Flash memory cell having reduced leakage current | Sheung-Hee Park, Dong-Hyuk Ju | 2005-05-24 |
| 6894925 | Flash memory cell programming method and system | Sheunghee Park, Sameer Haddad, Chi Chang, Ming Sang Kwan, Zhigang Wang | 2005-05-17 |
| 6878589 | Method and system for improving short channel effect on a floating gate device | Yue-Song He, Xin Guo | 2005-04-12 |
| 6867119 | Nitrogen oxidation to reduce encroachment | Yue-Song He, Zhi-Gang Wang | 2005-03-15 |
| 6852594 | Two-step source side implant for improving source resistance and short channel effect in deep sub-0.18μm flash memory technology | Zhigang Wang, Yue-Song He | 2005-02-08 |
| 6833297 | Method for reducing drain induced barrier lowering in a memory device | Yue-Song He, Nga-Ching Wong | 2004-12-21 |
| 6819615 | Memory device having resistive element coupled to reference cell for improved reliability | Wing Leung, John Wang | 2004-11-16 |
| 6781885 | Method of programming a memory cell | Sheung-Hee Park, Wing Leung | 2004-08-24 |
| 6773990 | Method for reducing short channel effects in memory cells and related structure | Yue-Song He, Kazuhiro Mizutani, Timothy Thurgate | 2004-08-10 |
| 6768683 | Low column leakage flash memory array | Sameer Haddad | 2004-07-27 |
| 6754109 | Method of programming memory cells | Sameer Haddad, Zhigang Wang, Sheung-Hee Park | 2004-06-22 |
| 6750157 | Nonvolatile memory cell with a nitridated oxide layer | Chi Chang, Narbeh Derhacobian | 2004-06-15 |
| 6737703 | Memory array with buried bit lines | Sameer Haddad, Yu Sun | 2004-05-18 |
| 6716698 | Virtual ground silicide bit line process for floating gate flash memory | Yue-Song He, Wei Zheng | 2004-04-06 |
| 6700201 | Reduction of sector connecting line capacitance using staggered metal lines | Yue-Song He, Sameer Haddad | 2004-03-02 |
| 6654285 | Method of matching core cell and reference cell source resistances | Jiang Li, Lee Cleveland | 2003-11-25 |
| 6646914 | Flash memory array architecture having staggered metal lines | Sameer Haddad | 2003-11-11 |
| 6593606 | Staggered bitline strapping of a non-volatile memory cell | Mark Randolph, Shane Hollmer, Pau-Ling Chen | 2003-07-15 |
| 6583479 | Sidewall NROM and method of manufacture thereof for non-volatile memory cells | Shane Hollmer, Pau-Ling Chen, Michael A. Van Buskirk, Masaaki Higashitani | 2003-06-24 |
| 6570211 | 2Bit/cell architecture for floating gate flash memory product and associated method | Yue-Song He, Zheng Wei | 2003-05-27 |
| 6541338 | Low defect density process for deep sub-0.18 &mgr;m flash memory technologies | Zhigang Wang, Yue-Song He | 2003-04-01 |
| 6538270 | Staggered bitline strapping of a non-volatile memory cell | Mark Randolph, Shane Hollmer, Pau-Ling Chen | 2003-03-25 |
| 6525959 | NOR array with buried trench source line | — | 2003-02-25 |