Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7157951 | Digital clock manager capacitive trim unit | Shawn K. Morrison | 2007-01-02 |
| 7117372 | Programmable logic device with decryption and structure for preventing design relocation | Stephen M. Trimberger, Walter N. Sze, Jennifer Wong | 2006-10-03 |
| 7117373 | Bitstream for configuring a PLD with encrypted design data | Stephen M. Trimberger, Walter N. Sze, Jennifer Wong, Kameswara K. Rao | 2006-10-03 |
| 7058177 | Partially encrypted bitstream method | Stephen M. Trimberger, Walter N. Sze | 2006-06-06 |
| 7046052 | Phase matched clock divider | Andrew K. Percey | 2006-05-16 |
| 7038519 | Digital clock manager having cascade voltage switch logic clock paths | Jennifer Wong | 2006-05-02 |
| 6981153 | Programmable logic device with method of preventing readback | Walter N. Sze, John M. Thendean, Stephen M. Trimberger, Jennifer Wong | 2005-12-27 |
| 6965675 | Structure and method for loading encryption keys through a test access port | Stephen M. Trimberger, John M. Thendean | 2005-11-15 |
| 6957340 | Encryption key for multi-key encryption in programmable logic device | Stephen M. Trimberger, Jennifer Wong | 2005-10-18 |
| 6931543 | Programmable logic device with decryption algorithm and decryption key | Walter N. Sze, Jennifer Wong, Stephen M. Trimberger, John M. Thendean, Kameswara K. Rao | 2005-08-16 |
| 6897676 | Configuration enable bits for PLD configurable blocks | — | 2005-05-24 |
| 6664837 | Delay line trim unit having consistent performance under varying process and temperature conditions | Kwansuhk Oh | 2003-12-16 |
| 6441641 | Programmable logic device with partial battery backup | Venu M. Kondapalli, Jane W. Sowards, Scott O. Frake, Jennifer Wong, F. Erich Goetting +2 more | 2002-08-27 |
| 6373779 | Block RAM having multiple configurable write modes for use in a field programmable gate array | Steven P. Young | 2002-04-16 |
| 6366117 | Nonvolatile/battery-backed key in PLD | Jennifer Wong, Scott O. Frake, Jane W. Sowards, Venu M. Kondapalli, F. Erich Goetting +2 more | 2002-04-02 |
| 6353921 | Hardwire logic device emulating any of two or more FPGAs | Edwin S. Law, Kiran B. Buch, Glenn A. Baxter | 2002-03-05 |
| 6346825 | Block RAM with configurable data width and parity for use in a field programmable gate array | Steven P. Young, Trevor J. Bauer | 2002-02-12 |
| 6282127 | Block RAM with reset to user selected value | Steven P. Young, Trevor J. Bauer | 2001-08-28 |
| 6134517 | Method of implementing a boundary scan chain | Glenn A. Baxter, Kiran B. Buch, Edwin S. Law | 2000-10-17 |
| 6120551 | Hardwire logic device emulating an FPGA | Edwin S. Law, Kiran B. Buch, Glenn A. Baxter | 2000-09-19 |
| 5991908 | Boundary scan chain with dedicated programmable routing | Glenn A. Baxter, Kiran B. Buch, Edwin S. Law | 1999-11-23 |