Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
EL

Edwin S. Law — 9 Patents

AMD: 7 patents #1,768 of 9,280Top 20%
E2E2Open: 2 patents #2 of 12Top 20%
Saratoga, CA: #909 of 2,933 inventorsTop 35%
California: #67,547 of 386,348 inventorsTop 20%
Overall (All Time): #535,341 of 4,157,543Top 15%
9 Patents All Time
Edwin S. Law has been granted 9 US patents while listed as an inventor at AMD. The first was granted in 1996 and the most recent in October 2012. Edwin S. Law ranks #535,341 of 4,157,543 US inventors in our database (top 12.9%). Patent records list Edwin S. Law in Saratoga, CA, US.

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8290833 Multi-stage supply chain management system with dynamic order placement Lou Ping Yang, Mingtang Thomas Yin, Siqing Wei, Johnson Lee 2012-10-16 $5,412,000
7529695 Multi-stage supply chain management system with dynamic order placement Lou Ping Yang, Mingtang Thomas Yin, Siqing Wei, Johnson Lee 2009-05-05
6353921 Hardwire logic device emulating any of two or more FPGAs Kiran B. Buch, Glenn A. Baxter, Raymond C. Pang 2002-03-05 $33,317,000
6226779 Programmable IC with gate array core and boundary scan capability Glenn A. Baxter, Kiran B. Buch 2001-05-01 $145,884,000
6134517 Method of implementing a boundary scan chain Glenn A. Baxter, Kiran B. Buch, Raymond C. Pang 2000-10-17 $134,625,000
6120551 Hardwire logic device emulating an FPGA Kiran B. Buch, Glenn A. Baxter, Raymond C. Pang 2000-09-19 $141,830,000
6071314 Programmable I/O cell with dual boundary scan Glenn A. Baxter, Kiran B. Buch 2000-06-06 $135,236,000
5991908 Boundary scan chain with dedicated programmable routing Glenn A. Baxter, Kiran B. Buch, Raymond C. Pang 1999-11-23 $39,764,000
5550839 Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays Kiran B. Buch, Jakong J. Chu 1996-08-27 $23,069,000