Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8040140 | Method and apparatus for identifying broken pins in a test socket | Christopher Wooten, Song Han, Douglas C. Kimbrough | 2011-10-18 |
| 7695986 | Method and apparatus for modifying process selectivities based on process state information | Matthew A. Purdy, Richard J. Markle | 2010-04-13 |
| 7282374 | Method and apparatus for comparing device and non-device structures | Kevin R. Lensing | 2007-10-16 |
| 7277824 | Method and apparatus for classifying faults based on wafer state data and sensor tool trace data | Kevin R. Lensing | 2007-10-02 |
| 7217578 | Advanced process control of thermal oxidation processes, and systems for accomplishing same | Michael J. McBride, Jesse C. Ramos, Mark E. Culp, Pirainder Lall | 2007-05-15 |
| 7197370 | Method and apparatus for dynamic adjustment of an active sensor list | — | 2007-03-27 |
| 6978187 | Method and apparatus for scheduling production lots based on lot and tool health metrics | — | 2005-12-20 |
| 6868353 | Method and apparatus for determining wafer quality profiles | — | 2005-03-15 |
| 6799311 | Batch/lot organization based on quality characteristics | — | 2004-09-28 |
| 6721616 | Method and apparatus for determining control actions based on tool health and metrology data | — | 2004-04-13 |
| 6617258 | Method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and system for accomplishing same | Thomas J. Sonderman | 2003-09-09 |
| 6593227 | Method and apparatus for planarizing surfaces of semiconductor device conductive layers | — | 2003-07-15 |
| 6582975 | Method of controlling the deposition of inter-level dielectric layers based upon electrical performance tests, and system for accomplishing same | — | 2003-06-24 |
| 6371135 | Method and apparatus for removing a particle from a surface of a semiconductor wafer | — | 2002-04-16 |