Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7216328 | Method and system for integrating cores in FPGA-based system-on-chip (SoC) | Reno L. Sanchez | 2007-05-08 |
| 7203632 | HDL co-simulation in a high-level modeling system | Roger B. Milne, Jeffrey D. Stroomer, Nabeel Shirazi, Haibing Ma, Jonathan B. Ballagh | 2007-04-10 |
| 7194705 | Simulation of integrated circuitry within a high-level modeling system using hardware description language circuit descriptions | Kumar Deepak, Singh Vinay Jitendra, Haibing Ma, Roger B. Milne, Nabeel Shirazi +2 more | 2007-03-20 |
| 7110935 | Method and system for modeling and automatically generating an electronic design from a system level environment | R. Brent Milne, Nabeel Shirazi, Jeffrey D. Stroomer | 2006-09-19 |
| 7085702 | Method and system for modeling and automatically generating an embedded system from a system-level environment | Jeffrey D. Stroomer | 2006-08-01 |
| 7058921 | Method and system for resource allocation in FPGA-based system-on-chip (SoC) | Reno L. Sanchez | 2006-06-06 |
| 7003751 | Specification of the hierarchy, connectivity, and graphical representation of a circuit design | Jeffrey D. Stroomer, Roger B. Milne, Jonathan B. Ballagh, Haibing Ma, Nabeel Shirazi | 2006-02-21 |
| 6941538 | Method and system for integrating cores in FPGA-based system-on-chip (SoC) | Reno L. Sanchez | 2005-09-06 |
| 6883147 | Method and system for generating a circuit design including a peripheral component connected to a bus | Jonathan B. Ballagh, Roger B. Milne, Jeffrey D. Stroomer, Eric R. Keller, Philip B. James-Roxby | 2005-04-19 |
| 6839879 | Method and system for time-stamping and managing electronic documents | — | 2005-01-04 |
| 6457164 | Hetergeneous method for determining module placement in FPGAs | Eric F. Dellinger, Sujoy Mitra, Sundararajarao Mohan, Cameron Patterson, Ralph D. Wittig | 2002-09-24 |
| 6430732 | Method for structured layout in a hardware description language | Cameron Patterson, Sujoy Mitra | 2002-08-06 |
| 6408422 | Method for remapping logic modules to resources of a programmable gate array | Cameron Patterson | 2002-06-18 |
| 6292925 | Context-sensitive self implementing modules | Eric F. Dellinger, Sujoy Mitra, Sundararajarao Mohan, Ralph D. Wittig | 2001-09-18 |
| 6260182 | Method for specifying routing in a logic module by direct module communication | Sundararajarao Mohan, Eric F. Dellinger, Sujoy Mitra, Ralph D. Wittig | 2001-07-10 |
| 6243851 | Heterogeneous method for determining module placement in FPGAs | Eric F. Dellinger, Sujoy Mitra, Sundararajarao Mohan, Cameron Patterson, Ralph D. Wittig | 2001-06-05 |
| 6237129 | Method for constraining circuit element positions in structured layouts | Cameron Patterson, Eric F. Dellinger, Sujoy Mitra, Sundararajarao Mohan, Ralph D. Wittig | 2001-05-22 |
| 6216258 | FPGA modules parameterized by expressions | Sundararajarao Mohan, Eric F. Dellinger, Sujoy Mitra, Ralph D. Wittig | 2001-04-10 |