Issued Patents All Time
Showing 26–50 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11422707 | Scheduling memory requests for a ganged memory device | — | 2022-08-23 |
| 11392441 | Error reporting for non-volatile memory modules | Kedarnath Balakrishnan, Vilas Sridharan | 2022-07-19 |
| 11200106 | Data integrity for persistent memory systems and the like | Kedarnath Balakrishnan, Kevin M. Lepak, Vilas Sridharan | 2021-12-14 |
| 11137941 | Command replay for non-volatile dual inline memory modules | Jing Wang, Kedarnath Balakrishnan | 2021-10-05 |
| 11099786 | Signaling for heterogeneous memory systems | Kedarnath Balakrishnan | 2021-08-24 |
| 10684969 | Command arbitration for high speed memory interfaces | Kedarnath Balakrishnan, Jackson Peng, Hideki Kanayama | 2020-06-16 |
| 10613764 | Speculative hint-triggered activation of pages in memory | Ravindra N. Bhargava, Philip Park, Vydhyanathan Kalyanasundharam | 2020-04-07 |
| 10503670 | Dynamic per-bank and all-bank refresh | Guanhao Shen, Ravindra N. Bhargava, Kedarnath Balakrishnan, Jing Wang | 2019-12-10 |
| 10403333 | Memory controller with flexible address decoding | Kevin M. Brandl, Thomas H. Hamilton, Hideki Kanayama, Kedarnath Balakrishnan, Guanhao Shen +1 more | 2019-09-03 |
| 10296230 | Scheduling memory requests with non-uniform latencies | Kedarnath Balakrishnan | 2019-05-21 |
| 10275352 | Supporting responses for memory types with non-uniform latencies on same channel | Kedarnath Balakrishnan | 2019-04-30 |
| 10198216 | Low power memory throttling | Kedarnath Balakrishnan, Kevin M. Brandl | 2019-02-05 |
| 10037150 | Memory controller with virtual controller mode | Kedarnath Balakrishnan | 2018-07-31 |
| 9965222 | Software mode register access for platform margining and debug | Kevin M. Brandl, Scott P. Murphy, Paramjit K. Lubana | 2018-05-08 |
| 8373447 | Method and apparatus of alternating service modes of an SOI process circuit | Joseph Kidd, Brian Amick, Ryan J. Hensley, Ronald L. Pettyjohn | 2013-02-12 |
| 6976204 | Circuit and method for correcting erroneous data in memory for pipelined reads | Eric G. Chambers, Dan S. Mudgett | 2005-12-13 |
| 6918016 | Method and apparatus for preventing data corruption during a memory access command postamble | — | 2005-07-12 |
| 6889334 | Multimode system for calibrating a data strobe delay for a memory read operation | Bruce A. Loyer, Pratik M. Mehta | 2005-05-03 |
| 6832327 | Apparatus and method for providing an external clock from a circuit in sleep mode in a processor-based system | Michael S. Quimby | 2004-12-14 |
| 6757755 | Peripheral interface circuit for handling graphics responses in an I/O node of a computer system | Tahsin Askar | 2004-06-29 |
| 6754779 | SDRAM read prefetch from multiple master devices | — | 2004-06-22 |
| 6721816 | Selecting independently of tag values a given command belonging to a second virtual channel and having a flag set among commands belonging to a posted virtual and the second virtual channels | Stephen C. Ennis | 2004-04-13 |
| 6681301 | System for controlling multiple memory types | Pratik M. Mehta | 2004-01-20 |
| 6678838 | Method to track master contribution information in a write buffer | — | 2004-01-13 |
| 6556952 | Performance monitoring and optimizing of controller parameters | — | 2003-04-29 |