Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6366117 | Nonvolatile/battery-backed key in PLD | Raymond C. Pang, Jennifer Wong, Scott O. Frake, Jane W. Sowards, Venu M. Kondapalli +2 more | 2002-04-02 |
| 6294930 | FPGA with a plurality of input reference voltage levels | Scott O. Frake, Venu M. Kondapalli, Steven P. Young | 2001-09-25 |
| 6289068 | Delay lock loop with clock phase shifter | Joseph H. Hassoun, John D. Logue | 2001-09-11 |
| 6262596 | Configuration bus interface circuit for FPGAS | David P. Schultz, Lawrence C. Hung | 2001-07-17 |
| 6204710 | Precision trim circuit for delay lines | Paul G. Hyland, Joseph H. Hassoun | 2001-03-20 |
| 6204691 | FPGA with a plurality of input reference voltage levels grouped into sets | Scott O. Frake, Venu M. Kondapalli, Steven P. Young | 2001-03-20 |
| 6204687 | Method and structure for configuring FPGAS | David P. Schultz, Lawrence C. Hung | 2001-03-20 |
| 6191613 | Programmable logic device with delay-locked loop | David P. Schultz, Lawrence C. Hung | 2001-02-20 |
| 6191614 | FPGA configuration circuit including bus-based CRC register | David P. Schultz, Lawrence C. Hung | 2001-02-20 |
| 6101132 | Block RAM with reset | Trevor J. Bauer | 2000-08-08 |
| 6086629 | Method for design implementation of routing in an FPGA using placement directives such as local outputs and virtual buffers | Edward S. McGettigan, Jennifer T. Tran | 2000-07-11 |
| 6049227 | FPGA with a plurality of I/O voltage levels | Scott O. Frake, Venu M. Kondapalli, Steven P. Young | 2000-04-11 |
| 5958026 | Input/output buffer supporting multiple I/O standards | Scott O. Frake, Venu M. Kondapalli | 1999-09-28 |
| 5912937 | CMOS flip-flop having non-volatile storage | Scott O. Frake | 1999-06-15 |
| 5877632 | FPGA with a plurality of I/O voltage levels | Scott O. Frake, Venu M. Kondapalli, Steven P. Young | 1999-03-02 |
| 5815404 | Method and apparatus for obtaining and using antifuse testing information to increase programmable device yield | David P. Schultz, David B. Squires | 1998-09-29 |
| 5764534 | Method for providing placement information during design entry | — | 1998-06-09 |
| 5744979 | FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses | — | 1998-04-28 |
| 5694047 | Method and system for measuring antifuse resistance | Venu M. Kondapalli, David P. Schultz | 1997-12-02 |
| 5672966 | High speed post-programming net packing method | Mikael Palczewski, David P. Schultz | 1997-09-30 |
| 5646547 | Logic cell which can be configured as a latch without static one's problem | — | 1997-07-08 |
| 5617021 | High speed post-programming net verification method | Wade K. Peterson, David P. Schultz | 1997-04-01 |
| 5500608 | Logic cell for field programmable gate array having optional internal feedback and optional cascade | Stephen M. Trimberger | 1996-03-19 |
| 5498979 | Adaptive programming method for antifuse technology | David B. Parlour, Stephen M. Trimberger, Edel M. Young | 1996-03-12 |
| 5399924 | Low current optional inverter | David P. Schultz | 1995-03-21 |