Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11031078 | SEU stabilized memory cells | Fengliang Xue, Fethi Dhaoui, Pavan Singaraju, Victor Nguyen, John McCollum | 2021-06-08 |
| 10523208 | Efficient lookup table modules for user-programmable integrated circuits | Jonathan W. Greene | 2019-12-31 |
| 10147485 | Circuits and methods for preventing over-programming of ReRAM-based memory cells | — | 2018-12-04 |
| 9990993 | Three-transistor resistive random access memory cells | John McCollum | 2018-06-05 |
| 9704573 | Three-transistor resistive random access memory cells | — | 2017-07-11 |
| 9170774 | Fast carry lookahead circuits | Marcel Derevlean, Jonathan W. Greene | 2015-10-27 |
| 9103880 | On-chip probe circuit for detecting faults in an FPGA | Jonathan W. Greene, Dirk Kannemacher, Theodore Speers | 2015-08-11 |
| 9000807 | On-chip probe circuit for detecting faults in an FPGA | Jonathan W. Greene, Dirk Kannemacher, Theodore Speers | 2015-04-07 |
| 8868820 | RAM block designed for efficient ganging | Jonathan W. Greene | 2014-10-21 |
| 8255854 | Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit | Kai Zhu | 2012-08-28 |
| 8244791 | Fast carry lookahead circuits | Marcel Derevlean, Jonathan W. Greene | 2012-08-14 |
| 7932745 | Inverting flip-flop for use in field programmable gate arrays | Fei Li, Jonathan W. Greene | 2011-04-26 |
| 7919977 | Circuits and methods for testing FPGA routing switches | Jonathan W. Greene, John McCollum | 2011-04-05 |
| 7884640 | PLD providing soft wakeup logic | Jonathan W. Greene, Gregory Bakker, Vidyadhara Bellippady, Theodore Speers | 2011-02-08 |
| 7816946 | Inverting flip-flop for use in field programmable gate arrays | Fei Li, Jonathan W. Greene | 2010-10-19 |
| 7804321 | Circuits and methods for testing FPGA routing switches | Jonathan W. Greene, John McCollum | 2010-09-28 |
| 7593268 | Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage | John McCollum, Robert M. Salter, III | 2009-09-22 |
| 7522453 | Non-volatile memory with source-side column select | Zhigang Wang, Gregory Bakker, Santosh Yachareni, Fethi Dhaoui, Vidyadhara Bellippady | 2009-04-21 |
| 7477071 | Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop | Alan B. Reynolds, Andrew W. Reynolds | 2009-01-13 |
| 7394286 | Field programmable gate array long line routing network | — | 2008-07-01 |
| 7365567 | Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop | Alan B. Reynolds, Andrew W. Reynolds | 2008-04-29 |
| 7212030 | Field programmable gate array long line routing network | — | 2007-05-01 |
| 7161841 | Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage | John McCollum | 2007-01-09 |
| 7106100 | Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop | Alan B. Reynolds, Andrew W. Reynolds | 2006-09-12 |
| 6777977 | Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop | Alan B. Reynolds, Andrew W. Reynolds | 2004-08-17 |