Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367534 | Method to operate the devices for real estate showings | Sri Sivanagaraju Kosanam, Vidyasagar Reddy Pentareddy, Ramesh Lingala, Adam Kuenzi, Matthew S. Hill +2 more | 2025-07-22 |
| 12154622 | ReRAM memory array that includes ReRAM memory cells having a ReRAM device and two series-connected select transistors that can be selected for erasing | Fethi Dhaoui, John McCollum, Fengliang Xue | 2024-11-26 |
| 11742005 | Selectively cross-coupled inverters, and related devices, systems, and methods | — | 2023-08-29 |
| 11355187 | Method for erasing a ReRAM memory cell | Fethi Dhaoui, John McCollum, Fengliang Xue | 2022-06-07 |
| 11031078 | SEU stabilized memory cells | Fengliang Xue, Fethi Dhaoui, Pavan Singaraju, John McCollum, Volker Hecht | 2021-06-08 |
| 10910050 | ReRAM memory cell having dual word line control | Fethi Dhaoui, John McCollum, Fengliang Xue | 2021-02-02 |
| 10872661 | ReRAM programming method including low-current pre-programming for program time reduction | Fengliang Xue, Fethi Dhaoui, John McCollum | 2020-12-22 |
| 10673778 | Transparent and efficient multi-destination TCP communications based on bit indexed explicit replication | Pierre Pfister, Pascal Thubert | 2020-06-02 |
| 10135756 | Transparent and efficient multi-destination TCP communications based on bit indexed explicit replication | Pierre Pfister, Pascal Thubert | 2018-11-20 |
| 7656219 | Unity gain voltage buffer with dual supply voltage for managing current consumption in low voltage applications | — | 2010-02-02 |
| 7180779 | Memory architecture with enhanced over-erase tolerant control gate scheme | Nicola Telecco | 2007-02-20 |
| 6809550 | High speed zero DC power programmable logic device (PLD) architecture | Saroj Pathak, James E. Payne, Harry Kuo | 2004-10-26 |