Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8676648 | Online map advertising | Brandon Badger, Michael S. Perrow | 2014-03-18 |
| 8560386 | Online map advertising | Brandon Badger, Michael S. Perrow | 2013-10-15 |
| 8249930 | Online map advertising | Brandon Badger, Mike Perrow | 2012-08-21 |
| 6809550 | High speed zero DC power programmable logic device (PLD) architecture | Saroj Pathak, Victor Nguyen, Harry Kuo | 2004-10-26 |
| 6744291 | Power-on reset circuit | Harry Kuo, Neville Ichhaporia, Jami Wang | 2004-06-01 |
| 6618289 | High voltage bit/column latch for Vcc operation | Saroj Pathak, Harry Kuo | 2003-09-09 |
| 6476785 | Drive circuit for liquid crystal display cell | Saroj Pathak | 2002-11-05 |
| 6411549 | Reference cell for high speed sensing in non-volatile memories | Saroj Pathak, Jagdish Pathak | 2002-06-25 |
| 6320454 | Low power voltage regulator circuit for use in an integrated circuit device | Saroj Pathak, Harry Kuo | 2001-11-20 |
| 6140993 | Circuit for transferring high voltage video signal without signal loss | Saroj Pathak, Glen Arnold Rosendale, Nianglamching Hangzo | 2000-10-31 |
| 6115305 | Method and apparatus for testing a video display chip | Saroj Pathak, Glen Arnold Rosendale, Nianglamching Hangzo | 2000-09-05 |
| 5999038 | Fuse circuit having zero power draw for partially blown condition | Saroj Pathak | 1999-12-07 |
| 5963496 | Sense amplifier with zero power idle mode | Saroj Pathak, Glen Arnold Rosendale, Nianglamching Hangzo | 1999-10-05 |
| 5946267 | Zero power high speed configuration memory | Saroj Pathak, Glen Arnold Rosendale, Nianglamching Hangzo | 1999-08-31 |
| 5936444 | Zero power power-on reset circuit | Jagdish Pathak, Saroj Pathak, Glen Arnold Rosendale, Nianglamching Hangzo | 1999-08-10 |
| 5781469 | Bitline load and precharge structure for an SRAM memory | Saroj Pathak | 1998-07-14 |
| 5731734 | Zero power fuse circuit | Jagdish Pathak, Saroj Pathak | 1998-03-24 |
| 5680346 | High-speed, non-volatile electrically programmable and erasable cell and method | Saroj Pathak | 1997-10-21 |
| 5493244 | Breakdown protection circuit using high voltage detection | Saroj Pathak, Glen Arnold Rosendale | 1996-02-20 |
| 5473500 | Electrostatic discharge circuit for high speed, high voltage circuitry | Saroj Pathak, Glen Arnold Rosendale | 1995-12-05 |
| 5440508 | Zero power high speed programmable circuit device architecture | Saroj Pathak | 1995-08-08 |
| 5383193 | Method for testing non-volatile memories | Saroj Pathak, Glen Arnold Rosendale | 1995-01-17 |