Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High speed zero DC power programmable logic device (PLD) architecture

High speed zero DC power programmable logic device (PLD) architecture

US Patent 6809550 · Granted Oct 26, 2004

Estimated economic value: $9,134,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Vehicle chassis crossmember apparatuses and methods thereof2025
Method to operate the devices for real estate showings2025
ReRAM memory array that includes ReRAM memory cells having a ReRAM device and tw2024
Selectively cross-coupled inverters, and related devices, systems, and methods2023
Method for erasing a ReRAM memory cell2022
SEU stabilized memory cells2021
ReRAM memory cell having dual word line control2021
ReRAM programming method including low-current pre-programming for program time 2020
Transparent and efficient multi-destination TCP communications based on bit inde2020
Transparent and efficient multi-destination TCP communications based on bit inde2018
Crossbar RRAM array radiation hardened application2015
Circuit for concurrent read operation and method therefor2015