Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6809550 | High speed zero DC power programmable logic device (PLD) architecture | James E. Payne, Victor Nguyen, Harry Kuo | 2004-10-26 |
| 6618289 | High voltage bit/column latch for Vcc operation | James E. Payne, Harry Kuo | 2003-09-09 |
| 6476785 | Drive circuit for liquid crystal display cell | James E. Payne | 2002-11-05 |
| 6411549 | Reference cell for high speed sensing in non-volatile memories | James E. Payne, Jagdish Pathak | 2002-06-25 |
| 6320454 | Low power voltage regulator circuit for use in an integrated circuit device | James E. Payne, Harry Kuo | 2001-11-20 |
| 6140993 | Circuit for transferring high voltage video signal without signal loss | James E. Payne, Glen Arnold Rosendale, Nianglamching Hangzo | 2000-10-31 |
| 6115305 | Method and apparatus for testing a video display chip | James E. Payne, Glen Arnold Rosendale, Nianglamching Hangzo | 2000-09-05 |
| 5999038 | Fuse circuit having zero power draw for partially blown condition | James E. Payne | 1999-12-07 |
| 5963496 | Sense amplifier with zero power idle mode | Glen Arnold Rosendale, James E. Payne, Nianglamching Hangzo | 1999-10-05 |
| 5946267 | Zero power high speed configuration memory | Glen Arnold Rosendale, James E. Payne, Nianglamching Hangzo | 1999-08-31 |
| 5936444 | Zero power power-on reset circuit | Jagdish Pathak, Glen Arnold Rosendale, James E. Payne, Nianglamching Hangzo | 1999-08-10 |
| 5917754 | Semiconductor memory having a current balancing circuit | Jagdish Pathak | 1999-06-29 |
| 5781469 | Bitline load and precharge structure for an SRAM memory | James E. Payne | 1998-07-14 |
| 5731734 | Zero power fuse circuit | Jagdish Pathak, James E. Payne | 1998-03-24 |
| 5680346 | High-speed, non-volatile electrically programmable and erasable cell and method | James E. Payne | 1997-10-21 |
| 5493244 | Breakdown protection circuit using high voltage detection | James E. Payne, Glen Arnold Rosendale | 1996-02-20 |
| 5473500 | Electrostatic discharge circuit for high speed, high voltage circuitry | James E. Payne, Glen Arnold Rosendale | 1995-12-05 |
| 5440508 | Zero power high speed programmable circuit device architecture | James E. Payne | 1995-08-08 |
| 5383193 | Method for testing non-volatile memories | Glen Arnold Rosendale, James E. Payne | 1995-01-17 |
| 5272674 | High speed memory sense amplifier with noise reduction | Glen Arnold Rosendale | 1993-12-21 |
| 5027320 | EPROM circuit having enhanced programmability and improved speed and reliability | Bruce L. Prickett, Jr. | 1991-06-25 |
| 4978905 | Noise reduction output buffer | David Hoff | 1990-12-18 |
| 4264828 | MOS Static decoding circuit | George Perlegos | 1981-04-28 |
| 4223394 | Sensing amplifier for floating gate memory devices | George Perlegos | 1980-09-16 |